LP2998/LP2998-Q1 DDR Termination Regulator
- SNVS521K December 2007 – August 2014 LP2998-Q1
  
  PRODUCTION DATA.

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DATA SHEET

LP2998/LP2998-Q1 DDR Termination Regulator

1 Features

AEC-Q100 Test Guidance with the following results (SO PowerPAD-8):
- Device HBM ESD Classification Level H1C
- Junction Temperature Range –40°C to 125°C
1.35 V Minimum V_DDQ
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology
Suspend to Ram (STR) Functionality
Low External Component Count
Thermal Shutdown

2 Applications

DDR1, DDR2, DDR3, and DDR3L Termination Voltage
Automotive Infotainment
FPGA
Industrial/Medical PC
SSTL-18, SSTL-2, and SSTL-3 Termination
HSTL Termination

3 Description

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with V_DDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a V_REF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the V_TT output will tri-state providing a high impedance output, but, V_REF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LP2998	SO PowerPAD™ (8)	4.89 mm x 3.90 mm
LP2998	SOIC (8)	4.90 mm x 3.91 mm
LP2998-Q1	SO PowerPAD™ (8)	4.89 mm x 3.90 mm

For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

5 Revision History

Changes from J Revision (December 2013) to K Revision

Added DDR3 support throughout datasheetGo
Changed formatting to match new TI datasheet guidelines; added Device Information and Handling Ratings tables, Power Supply, Layout Examples, and Device and Documentation Support sections; reformatted Detailed Description and Application and Implementation sections. Go
Changed Electrical Char table condition statement Go

Changes from I Revision (April 2013) to J Revision

Added AEC-Q100 Test GuidanceGo
Changed layout of National Data Sheet to TI formatGo

6 Pin Configuration and Functions

SO PowerPAD

8-LEAD DDA

TOP VIEW

SOIC

8-LEAD D

TOP VIEW

Pin Functions

PIN
NUMBER	TYPE	DESCRIPTION
1	GND	Ground
2	SD	Shutdown
3	VSENSE	Feedback pin for regulating V_TT.
4	VREF	Buffered internal reference voltage of V_DDQ/2
5	VDDQ	Input for internal reference equal to V_DDQ/2
6	AVIN	Analog input pin
7	PVIN	Power input pin
8	VTT	Output voltage for connection to termination resistors
	EP	Exposed pad thermal connection. Connect to Ground.

6.1 Pin Descriptions

AVIN AND PVIN	AVIN and PVIN are the input supply pins for the LP2998. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5 V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3 V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where V_TT is tri-stated and V_REF remains active.
VDDQ	VDDQ is the input used to create the internal reference voltage for regulating V_TT. The reference voltage is generated from a resistor divider of two internal 50 kΩ resistors. This ensures that V_TT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5 V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5 V signal, which will create a 1.25 V termination voltage at V_TT (See Electrical Characteristics Table for exact values of V_TT over temperature).
V_SENSE	The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to V_TT in a long plane. If the output voltage was regulated only at the output of the LP2998 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The V_SENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the V_SENSE pin must still be connected to V_TT. Care should be taken when a long V_SENSE trace is implemented in close proximity to the memory. Noise pickup in the V_SENSE trace can cause problems with precise regulation of V_TT. A small 0.1 uF ceramic capacitor placed next to the V_SENSE pin can help filter any high frequency signals and preventing errors.
SHUTDOWN	The LP2998 contains an active low shutdown pin that can be used to tri-state VTT. During shutdown V_TT should not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current of the LP2998 will drop, however, V_DDQ will always maintain its constant impedance of 100 kΩ for generating the internal reference. Therefore, to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open.
V_REF	V_REF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from V_REF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 µF to 0.01 µF is recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality.
V_TT	V_TT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2998 is designed to handle peak transient currents of up to ± 3 A with a fast transient response. The maximum continuous current is a function of V_IN and can be viewed in the Typical Characteristics section. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the LP2998 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than V_TT will tri-state until the part returns below the hysteretic trip-point.

7 Specifications

7.1 Absolute Maximum Ratings ⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
AVIN to GND	−0.3	6	V
PVIN to GND	–0.3	AVIN	V
VDDQ⁽³⁾	−0.3	6	V
Junction temperature		150	°C
Lead temperature (soldering, 10 sec)		260	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.

7.2 Handling Ratings: LP2998

			MIN	MAX	UNIT
T_stg	Storage temperature range		−65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	−1000	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Handling Ratings: LP2998-Q1

				MIN	MAX	UNIT
T_stg	Storage temperature range			−65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		−1000	1000	V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. The LP2998-Q1 is rated at AEC-Q100 ESD HBM Classification Level H1C.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Junction temperature⁽¹⁾	–40	125	°C
AVIN to GND	2.2	5.5	V
PVIN supply voltage	0	AVIN	V
SD input voltage	0	AVIN	V

7.5 Thermal Information

THERMAL METRIC⁽¹⁾		LP2998/LP2998-Q1	LP2998	UNIT
		SO PowerPAD	SOIC
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	43	151	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics

Typical limits tested at T_J = 25°C. Minimum and maximum limits apply over the full operating junction temperature range (T_J = –40°C to 125°C).⁽²⁾ Unless otherwise specified, AVIN = PVIN = 2.5 V, VDDQ = 2.5 V.⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_REF	V_REF voltage (DDR I)	VIN = VDDQ = 2.3 V	1.135	1.158	1.185	V
		VIN = VDDQ = 2.5 V	1.235	1.258	1.285
		VIN = VDDQ = 2.7 V	1.335	1.358	1.385
	V_REF voltage (DDR II)	PVIN = VDDQ = 1.7 V	0.837	0.860	0.887
		PVIN = VDDQ = 1.8 V	0.887	0.910	0.937
		PVIN = VDDQ = 1.9 V	0.936	0.959	0.986
	V_REF Voltage (DDR III)	PVIN = VDDQ = 1.35V	0.669	0.684	0.699
		PVIN = VDDQ = 1.5V	0.743	0.758	0.773
		PVIN = VDDQ = 1.6V	0.793	0.808	0.823
Z_VREF	V_REF Output Impedance	I_REF = –30 to 30 µA		2.5		kΩ
V_TT	V_TT Output Voltage (DDR I) ⁽⁶⁾	I_OUT = 0 A				V
		VIN = VDDQ = 2.3 V	1.120	1.159	1.190
		VIN = VDDQ = 2.5 V	1.210	1.259	1.290
		VIN = VDDQ = 2.7 V	1.320	1.359	1.390
		I_OUT = ±1.5 A
		VIN = VDDQ = 2.3 V	1.125	1.159	1.190
		VIN = VDDQ = 2.5 V	1.225	1.259	1.290
		VIN = VDDQ = 2.7 V	1.325	1.359	1.390
	V_TT Output Voltage (DDR II) ⁽⁶⁾	I_OUT = 0 A, AVIN = 2.5 V				V
		PVIN = VDDQ = 1.7 V	0.822	0.856	0.887
		PVIN = VDDQ = 1.8 V	0.874	0.908	0.939
		PVIN = VDDQ = 1.9 V	0.923	0.957	0.988
		I_OUT = ±0.5A, AVIN = 2.5 V
		PVIN = VDDQ = 1.7 V	0.820	0.856	0.890
		PVIN = VDDQ = 1.8 V	0.870	0.908	0.940
		PVIN = VDDQ = 1.9 V	0.920	0.957	0.990
	V_TT Output Voltage (DDR III) ⁽⁶⁾	I_OUT = 0A, AVIN = 2.5 V				V
		PVIN = VDDQ = 1.35V	0.656	0.677	0.698
		PVIN = VDDQ = 1.5 V	0.731	0.752	0.773
		PVIN = VDDQ = 1.6 V	0.781	0.802	0.823
		I_OUT = 0.2 A, AVIN = 2.5V PVIN = VDDQ = 1.35V	0.667	0.688	0.710
		I_OUT = -0.2A, AVIN = 2.5V PVIN = VDDQ = 1.35V	0.641	0.673	0.694
		I_OUT = 0.4 A, AVIN = 2.5 V PVIN = VDDQ = 1.5 V	0.740	0.763	0.786
		I_OUT = –0.4 A, AVIN = 2.5 V PVIN = VDDQ = 1.5 V	0.731	0.752	0.773
		I_OUT = 0.5 A, AVIN = 2.5 V PVIN = VDDQ = 1.6 V	0.790	0.813	0.836
		I_OUT = –0.5 A, AVIN = 2.5 V PVIN = VDDQ = 1.6 V	0.781	0.802	0.823
VOS_Vtt	V_TT Output Voltage Offset (V_REF – V_TT) for DDR I ⁽⁶⁾	I_OUT = 0 A	–30	0	30	mV
		I_OUT = –1.5 A	–30	0	30
		I_OUT = 1.5 A	–30	0	30
	V_TT Output Voltage Offset (V_REF – V_TT) for DDR II ⁽⁶⁾	I_OUT = 0 A	–30	0	30
		I_OUT = –0.5 A	–30	0	30
		I_OUT = 0.5 A	–30	0	30
	V_TT Output Voltage Offset (V_REF – V_TT) for DDR III ⁽⁶⁾	I_OUT = 0 A	–30	0	30
		I_OUT = ±0.2 A	–30	0	30
		I_OUT = ±0.4 A	–30	0	30
		I_OUT = ±0.5 A	–30	0	30
I_Q	Quiescent Current ⁽⁴⁾	I_OUT = 0 A		320	500	µA
Z_VDDQ	VDDQ Input Impedance			100		kΩ
I_SD	Quiescent current in shutdown ⁽⁴⁾	SD = 0 V		115	150	µA
I_{Q_SD}	Shutdown leakage current	SD = 0 V		2	5	µA
V_IH	Minimum Shutdown High Level		1.9			V
V_IL	Maximum Shutdown Low Level				0.8	V
Iv	V_TT leakage current in shutdown	SD = 0 V V_TT = 1.25 V		1	10	µA
I_SENSE	V_SENSE Input current			13		nA
T_SD	Thermal Shutdown ⁽⁵⁾			165		°C
T_{SD_HYS}	Thermal Shutdown Hysteresis			10		°C

(1) At elevated temperatures, devices must be derated based on thermal resistance.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate Texas Instruments' Average Outgoing Quality Level (AOQL).

(3) VIN is defined as VIN = AVIN = PVIN.

(4) Quiescent current defined as the current flow into AVIN.

(5) The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction to ambient thermal resistance, R_θJA, and the ambient temperature, T_A. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown.

(6) V_TT load regulation is tested by using a 10 ms current pulse and measuring V_TT.

7.7 Typical Characteristics

Unless otherwise specified AVIN = PVIN = 2.5 V.

Figure 1. I_Q vs AV_IN In SD

Figure 3. V_IH and V_IL

Figure 5. V_REF vs V_DDQ

Figure 7. I_SD vs AV_IN Over Temperature

V_DDQ = 2.5 V	PV_IN = 1.8 V

Figure 9. Maximum Sourcing Current vs AV_IN

V_DDQ = 2.5 V	PV_IN = 3.3 V

Figure 11. Maximum Sourcing Current vs AV_IN

V_DDQ = 1.8 V	PV_IN = 1.8 V

Figure 13. Maximum Sourcing Current vs AV_IN

	V_DDQ = 1.8 V	PV_IN = 3.3 V

Figure 15. Maximum Sourcing Current vs AV_IN

Figure 2. I_Q vs Av_IN

Figure 4. V_REF vs I_REF

Figure 6. V_TT vs V_DDQ

Figure 8. I_Q vs AV_IN Over Temperature

V_DDQ = 2.5 V	PV_IN = 2.5 V

Figure 10. Maximum Sourcing Current vs AV_IN

V_DDQ = 2.5 V

Figure 12. Maximum Sinking Current vs AV_IN

V_DDQ = 1.8 V

Figure 14. Maximum Sinking Current vs AV_IN

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

The LP2998 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-18. The output, V_TT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2998 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2998 to provide a termination solution for DDR3-SDRAM and DDR3L-SDRAM memory.

8.4 Device Functional Modes

The LP2998 can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one R_S series resistor from the chipset to the memory and one R_T termination resistor. Typical values for R_S and R_T are 25 Ω, although these can be changed to scale the current requirements from the LP2998. This implementation can be seen below in Figure 16.

Figure 16. SSTL-Termination Scheme