SNVU663A June 2019 – May 2021 LP87524-Q1 , LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
Each of the bucks and GPOs on the LP87524B/J/P-Q1 can be set to startup and shutdown in a specific sequence. To configure the desired sequence the STARTUP_DELAY and SHUTDOWN_DELAY fields for each output need to be set to a value between 0x0 and 0xF. The delay time that this value corresponds to depends on the DOUBLE_DELAY bit and the HALF_DELAY bit located in the CONFIG register. A value of 0 on both of these bits will allow a delay ranging from 0 ms to 15 ms with 1 ms steps. Figure 3-1 shows default startup and shutdown sequence programmed to OTP, in this case with EN1 signal. Refer to the datasheet for a full description of all registers and their settings.