SNVU881 January   2024 LP8733

 

  1.   1
  2.   Trademarks
  3.   Technical Reference Manual
  4. 1Introduction
  5. 2OTP Memory Device Settings
  6. 3Power-up and Power Down Sequence
  7. 4Register Bits Loaded From OTP Memory
  8. 5Revision History

3 Power-up and Power Down Sequence

This section shows the power-up and power-down sequence for the device. The power-up and power-down delays for each rail are shown in Figure 3-1.


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Figure 3-1 LP87334FPower-up and Power Down Sequence