SPRAC90G August   2021  – October 2022 66AK2G12 , AM2431 , AM2432 , AM2434 , AM2631 , AM2632 , AM2634 , AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359 , AM4372 , AM4376 , AM4377 , AM4378 , AM4379 , AM5706 , AM5708 , AM5716 , AM5718 , AM5726 , AM5728 , AM5729 , AM5746 , AM5748 , AM623 , AM625 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442 , AM6526 , AM6528 , AM6546 , AM6548

 

  1.   PRU-ICSS Feature Comparison
  2.   Trademarks
  3. 1Introduction
    1. 1.1 PRU-ICSS: The Programmable Real-time Unit and Industrial Communication Subsystem
    2. 1.2 PRU_ICSSG: The Programmable Real-time Unit and Industrial Communication Subsystem - Gigabit
    3. 1.3 PRUSS: The Programmable Real-time Unit Subsystem
    4. 1.4 PRU Subsystem Feature Comparison
  4. 2PRU-ICSS Feature Comparison
  5. 3PRU_ICSSG Feature Comparison
  6. 4PRUSS Features
  7. 5References
  8. 6Revision History

PRU-ICSS Feature Comparison

Table 2-1 PRU-ICSS Feature Comparison
Features AM335x AM437x AM570x AM571x AM572x AM574x K2G AM263x
PRU-ICSS1 PRU-ICSS1 PRU-ICSS0 2x PRU-ICSS (1) 2x PRU-ICSS (1) 2x PRU-ICSS (1) 2x PRU-ICSS
(1)
2x PRU-ICSS (1) 1x PRU-ICSS
Number of PRU cores 2 2 2 2 2 2 2 2 2
Max Frequency 200 MHz 225 MHz (2) 225 MHz (2) 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
IRAM size (per PRU core) 8 KB 12 KB 4 KB 12 KB 12 KB 12 KB 12 KB 16 KB 12 KB
DRAM size (2 DRAMs per PRU-ICSS) 8 KB 8 KB 4 KB 8 KB 8 KB 8 KB 8 KB 8 KB 8 KB
Shared DRAM size 12 KB 32 KB 0 KB 32KB 32KB 32KB 32 KB 64KB w/ ECC 32 KB
General Purpose Input
(per PRU core)
Direct; or 16-bit parallel capture; or 28-bit shift Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift Direct; or 16-bit parallel capture; or 28- bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta Direct; or 16-bit parallel capture; or 28-bit shift; or 3 ch EnDat 2.2; or 9 ch Sigma Delta
General Purpose Output
(per PRU core)
Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out Direct; or Shift out
GPI Pins (PRU0, PRU1) 17, 17 13, 0 20, 20 0/21(3), 21/17 0/21(3), 21/21 21, 21 21, 21 20, 20 17, 20
GPO Pins (PRU0, PRU1) 16, 16 12, 0 20, 20 0/21(3), 21/17 0/21(3), 21/21 21, 21 21, 21 20, 20 17, 20
MPY/MAC Y Y Y Y Y Y Y Y Y
Scratchpad Y (3 banks) Y (3 banks) N Y (3 banks) Y (3 banks) Y (3 banks) Y (3 banks) Y (3 banks) Y (3 banks)
CRC16/32 0 2 2 2 2 2 (4) 2 2 2
INTC 1 1 1 1 1 1 1 1 1
Peripherals
     UART 1 1 1 1 / not pinned out (5) 1 1 1 1 1
     eCAP 1 1 not pinned out 1 / not pinned out (5) 1 1 1 1 1
     IEP 1 1 not pinned out 1 / not pinned out (5) 1 1 1 1 1
     MII_RT 2 2 not pinned out 2 2 2 2 2 2
     MDIO 1 1 not pinned out 1 1 1 1 1 1
The name PRU-ICSS and PRUSS are used interchangeably throughout the AM57xx and K2G documentation to describe the Programmable Real-Time Unit (PRU) and Industrial Communication Subsystem.
The default frequency for AM437x is 200 MHz. However, the max frequency 225 MHz is achievable through display PLL CLKOUT. For DSS limitations when configuring this PLL for frequencies >200 MHz, see the AM437x Sitara Processors Technical Reference Manual.
AM571x and AM570x PRU-ICSS1 does not pin out the PRU0 core GPIs/GPOs. The other AM571x and AM570x PRU cores (PRU-ICSS1 PRU1, PRU-ICSS2 PRU0, PRU-ICSS2 PRU1) each pin out the number of GPIs/GPOs is listed in Table 2-1.
AM572x SR1.1 does not have CRC16/32. Within the AM57x family, this feature is only available in AM572x SR2.0, AM571x, and AM570x.
AM570x PRU-ICSS2 does not pin out these sub-modules. However, they are pinned out on the other AM570x subsystem (PRU-ICSS1).