SPRACA7A October   2017  – September 2022 TMS320F28075 , TMS320F28075-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   C2000™ Hardware Built-In Self-Test
  2.   Trademarks
  3. 1Introduction
    1. 1.1 HWBIST Overview
      1. 1.1.1 HWBIST Working In-System
    2. 1.2 HWBIST Failure Response
    3. 1.3 Advantages of Using HWBIST In-System
  4. 2Using HWBIST In-System
    1. 2.1 Fundamental HWBIST Operation
      1. 2.1.1 Initializing the HWBIST Controller
      2. 2.1.2 Executing HWBIST
        1. 2.1.2.1 Executing HWBIST Micro-Run
        2. 2.1.2.2 Executing HWBIST Full-Run
      3. 2.1.3 Error Management
    2. 2.2 Managing HWBIST on Dual-Core Device
      1. 2.2.1 Semaphore Management
      2. 2.2.2 Interprocessor Communications
    3. 2.3 System Considerations When Using HWBIST
      1. 2.3.1 Interrupt Latency
      2. 2.3.2 Power Considerations
      3. 2.3.3 HWBIST Memory Requirements
      4. 2.3.4 Injecting Errors
    4. 2.4 Debugging HWBIST In-System
  5. 3References
  6. 4Revision History

1 Introduction

HWBIST refers to circuitry and scan patterns generated by an ATPG tool used to screen out logic failures within the targeted circuitry. This methodology is used extensively in semiconductor device testing. All C2000 devices make use of some level of hardware-assisted test during device manufacturing. Some of the newer C2000 devices support customer use of this test technology as part of their system test, to test the integrity of the CPUs (US 8,799,713 B2). This document describes how and why to make use of HWBIST at a system level.

Table 1-1 lists the terms and abbreviations used in this application report.

Table 1-1 Terms and Abbreviations
Abbreviation Term
ATPG Automatic test pattern generation
BIST Built-In Self-Test
Capture The embedded circuitry capturing the results of the changing logic as the seeds are clocked through the logic under test
C28x The name of the core 32-bit CPU in TMS320C28x devices
CS Code Composer Studio™
CLA Control Law Accelerator
Context restore The process of restoring the central processing unit (CPU) registers and status flags after completing a hardware BIST micro-run. This is performed by the software.
Context save The process of saving the CPU registers and status flags before starting a hardware BIST micro-run. This is performed by the software.
Core bounding The CPU core is disconnected from peripherals and interrupt signals during a micro-run test. After the test, the core is reconnected to these signals.
Coverage The percentage of the CPU logic that is covered by the hardware BIST.
CPU Central processing unit
CRC Cyclical redundancy check
DC Diagnostic coverage
Flash Nonvolatile on-chip memory
FPU Floating point unit
HWBIST Hardware Built-In Self-Test
ISR Interrupt service routine
JTAG Joint test action group. JTAG is a scan-based communications protocol (like I2C) which allows for scanning to either test circuitry or emulation circuitry.
Micro-run Execution of a portion of a full HWBIST test execution. The HWBIST is designed to support executing the full coverage test in pieces to better manage interrupt latency and power. These micro-runs must be executed in smaller time-slices for more efficient task scheduling. During a micro-run, the CPU is isolated from all peripherals and memory. In addition, interrupts are logged by the HWBIST controller.
MISR Multiple-input signature-register
NMI Nonmaskable interrupt
PEST Periodic self-test
PLL Phase-locked loop
POR Power-on reset
POST Power-on self-test
RAM Random access memory
ROM Read-only memory
Seed Initial states which are loaded into the circuitry using scan paths, so that the circuitry starts out in a known state before testing begins
Semaphore A mechanism to acquire write access to certain self-test registers by CPU1 or CPU2 used on multi-core devices
SDL Software Diagnostic Library
STL Self-Test Library
TMU Trigonometric math unit
TRM Technical reference manual
VCU Viterbi and complex math unit

On C2000 devices that have HWBIST, the HWBIST targets the C28x CPU and the FPU, VCU, CRC, and TMU accelerators. Also included is the emulation analysis circuitry, which manages communications between these processing elements and the emulator, as well as manages features like breakpoints, watch points, and single stepping.

The HWBIST does not target the rest of the logic on the device. The other logic on the device may be tested with other self-test or diagnostic mechanisms as described in the device-specific safety manual.

For the availability of HWBIST, see the device-specific data sheet. You can also check the documents below for HWBIST and other functional safety features and collateral:

While this document focuses on HWBIST, for functional safety compliant C2000 devices without HWBIST (like those in the F28004x device family), a C28x Self-Test Library (C28x STL) is provided to test the integrity of the CPU logic using a software-based method. Similarly, HWBIST does not cover the Control Law Accelerator (CLA), so for devices with CLA, a separate CLA Self-Test Library (CLA STL) is available. These libraries are provided upon request—reach out to your local TI Sales Person to request access.