SPRACN0F October   2021  – March 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.    The Essential Guide for Developing With C2000™ Real-Time Microcontrollers
  2.   Trademarks
  3. 1C2000 and Real-Time Control
    1. 1.1 Getting Started Resources
    2. 1.2 Processing
    3. 1.3 Control
    4. 1.4 Sensing
    5. 1.5 Interface
    6. 1.6 Functional Safety
  4. 2Sensing Key Technologies
    1. 2.1 Accurate Digital Domain Representation of Analog Signals
      1. 2.1.1 Value Proposition
      2. 2.1.2 In Depth
      3. 2.1.3 Device List
      4. 2.1.4 Hardware Platforms and Software Examples
      5. 2.1.5 Documentation
    2. 2.2 Optimizing Acquisition Time vs Circuit Complexity for Analog Inputs
      1. 2.2.1 Value Proposition
      2. 2.2.2 In Depth
      3. 2.2.3 Device List
      4. 2.2.4 Hardware Platforms and Software Examples
      5. 2.2.5 Documentation
    3. 2.3 Hardware Based Monitoring of Dual-Thresholds Using a Single Pin Reference
      1. 2.3.1 Value Proposition
      2. 2.3.2 In Depth
      3. 2.3.3 Device List
      4. 2.3.4 Hardware Platforms and Software Examples
      5. 2.3.5 Documentation
    4. 2.4 Resolving Tolerance and Aging Effects During ADC Sampling
      1. 2.4.1 Value Proposition
      2. 2.4.2 In Depth
      3. 2.4.3 Device List
      4. 2.4.4 Hardware Platforms and Software Examples
      5. 2.4.5 Documentation
    5. 2.5 Realizing Rotary Sensing Solutions Using C2000 Configurable Logic Block
      1. 2.5.1 Value Proposition
      2. 2.5.2 In Depth
      3. 2.5.3 Device List
      4. 2.5.4 Hardware Platforms and Software Examples
      5. 2.5.5 Documentation
    6. 2.6 Smart Sensing Across An Isolation Boundary
      1. 2.6.1 Value Proposition
      2. 2.6.2 In Depth
      3. 2.6.3 Device List
      4. 2.6.4 Hardware Platforms and Software Examples
      5. 2.6.5 Documentation
    7. 2.7 Enabling Intra-Period Updates in High Bandwidth Control Topologies
      1. 2.7.1 Value Proposition
      2. 2.7.2 In Depth
      3. 2.7.3 Device List
      4. 2.7.4 Hardware Platforms and Software Examples
      5. 2.7.5 Documentation
    8. 2.8 Accurate Monitoring of Real-Time Control System Events Without the Need for Signal Conditioning
      1. 2.8.1 Value Proposition
      2. 2.8.2 In Depth
      3. 2.8.3 Device List
      4. 2.8.4 Hardware Platforms and Software Examples
      5. 2.8.5 Documentation
  5. 3Processing Key Technologies
    1. 3.1 Accelerated Trigonometric Math Functions
      1. 3.1.1 Value Proposition
      2. 3.1.2 In Depth
      3. 3.1.3 Device List
      4. 3.1.4 Hardware Platforms and Software Examples
      5. 3.1.5 Documentation
    2. 3.2 Fast Onboard Integer Division
      1. 3.2.1 Value Proposition
      2. 3.2.2 In Depth
      3. 3.2.3 Device List
      4. 3.2.4 Hardware Platforms and Software Platforms
      5. 3.2.5 Documentation
    3. 3.3 Hardware Support for Double-Precision Floating-Point Operations
      1. 3.3.1 Value Proposition
      2. 3.3.2 In Depth
      3. 3.3.3 Device List
      4. 3.3.4 Hardware Platforms and Software Examples
      5. 3.3.5 Documentation
    4. 3.4 Increasing Control Loop Bandwidth With An Independent Processing Unit
      1. 3.4.1 Value Proposition
      2. 3.4.2 In Depth
      3. 3.4.3 Device List
      4. 3.4.4 Hardware Platforms and Software Examples
      5. 3.4.5 Documentation
    5. 3.5 Flexible System Interconnect: C2000 X-Bar
      1. 3.5.1 Value Proposition
      2. 3.5.2 In Depth
      3. 3.5.3 Device List
      4. 3.5.4 Hardware Platforms and Software Examples
      5. 3.5.5 Documentation
    6. 3.6 Improving Control Performance With Nonlinear PID Control
      1. 3.6.1 Value Proposition
      2. 3.6.2 In Depth
      3. 3.6.3 Device List
      4. 3.6.4 Hardware Platforms and Software Examples
      5. 3.6.5 Documentation
    7. 3.7 Understanding Flash Memory Performance In Real-Time Control Applications
      1. 3.7.1 Value Proposition
      2. 3.7.2 In Depth
      3. 3.7.3 Device List
      4. 3.7.4 Hardware Platforms and Software Examples
      5. 3.7.5 Documentation
    8. 3.8 Deterministic Program Execution With the C28x DSP Core
      1. 3.8.1 Value Proposition
      2. 3.8.2 In Depth
      3. 3.8.3 Device List
      4. 3.8.4 Hardware Platforms and Software Examples
      5. 3.8.5 Documentation
    9. 3.9 Efficient Live Firmware Updates (LFU) and Firmware Over-The-Air (FOTA) updates
      1. 3.9.1 Value Proposition
      2. 3.9.2 In Depth
      3. 3.9.3 Device List
      4. 3.9.4 Hardware Platforms and Software Examples
      5. 3.9.5 Documentation
  6. 4Control Key Technologies
    1. 4.1 Reducing Limit Cycling in Control Systems With C2000 HRPWMs
      1. 4.1.1 Value Proposition
      2. 4.1.2 In Depth
      3. 4.1.3 Device List
      4. 4.1.4 Hardware Platforms and Software Examples
      5. 4.1.5 Documentation
    2. 4.2 Shoot Through Prevention for Current Control Topologies With Configurable Deadband
      1. 4.2.1 Value Proposition
      2. 4.2.2 In Depth
      3. 4.2.3 Device List
      4. 4.2.4 Documentation
    3. 4.3 On-Chip Hardware Customization Using the C2000 Configurable Logic Block
      1. 4.3.1 Value Proposition
      2. 4.3.2 In Depth
      3. 4.3.3 Device List
      4. 4.3.4 Hardware Platforms and Software Examples
      5. 4.3.5 Documentation
    4. 4.4 Fast Detection of Over and Under Currents and Voltages
      1. 4.4.1 Value Proposition
      2. 4.4.2 In Depth
      3. 4.4.3 Device List
      4. 4.4.4 Hardware Platforms and Software Examples
      5. 4.4.5 Documentation
    5. 4.5 Improving System Power Density With High Resolution Phase Control
      1. 4.5.1 Value Proposition
      2. 4.5.2 In Depth
      3. 4.5.3 Device List
      4. 4.5.4 Hardware Platforms and Software Examples
      5. 4.5.5 Documentation
    6. 4.6 Safe and Optimized PWM Updates in High-Frequency, Multi-Phase and Variable Frequency Topologies
      1. 4.6.1 Value Proposition
      2. 4.6.2 In Depth
      3. 4.6.3 Device List
      4. 4.6.4 Hardware Platforms and Software Examples
      5. 4.6.5 Documentation
    7. 4.7 Solving Event Synchronization Across Multiple Controllers in Decentralized Control Systems
      1. 4.7.1 Value Proposition
      2. 4.7.2 In Depth
      3. 4.7.3 Device List
      4. 4.7.4 Hardware Platforms and Software Examples
      5. 4.7.5 Documentation
  7. 5Interface Key Technologies
    1. 5.1 Direct Host Control of C2000 Peripherals
      1. 5.1.1 Value Proposition
      2. 5.1.2 In Depth
        1. 5.1.2.1 HIC Bridge for FSI Applications
        2. 5.1.2.2 HIC Bridge for Position Encoder Applications Using CLB
      3. 5.1.3 Device List
      4. 5.1.4 Hardware Platforms and Software Examples
      5. 5.1.5 Documentation
    2. 5.2 Securing External Communications and Firmware Updates With an AES Engine
      1. 5.2.1 Value Proposition
      2. 5.2.2 In Depth
      3. 5.2.3 Device List
      4. 5.2.4 Hardware Platforms and Software Examples
      5. 5.2.5 Documentation
    3. 5.3 Distributed Real-Time Control Across an Isolation Boundary
      1. 5.3.1 Value Proposition
      2. 5.3.2 In Depth
      3. 5.3.3 Device List
      4. 5.3.4 Hardware Platforms and Software Examples
      5. 5.3.5 Documentation
    4. 5.4 Custom Tests and Data Pattern Generation Using the Embedded Pattern Generator (EPG)
      1. 5.4.1 Value Proposition
      2. 5.4.2 In Depth
      3. 5.4.3 Device List
      4. 5.4.4 Hardware Platforms and Software Examples
      5. 5.4.5 Documentation
  8. 6Safety Key Technologies
    1. 6.1 Non-Intrusive Run Time Monitoring and Diagnostics as Part of the Control Loop
      1. 6.1.1 Value Proposition
      2. 6.1.2 In Depth
      3. 6.1.3 Device List
      4. 6.1.4 Hardware Platforms and Software Examples
      5. 6.1.5 Documentation
    2. 6.2 Hardware Built-In Self-Test of the C28x CPU
      1. 6.2.1 Value Proposition
      2. 6.2.2 In Depth
      3. 6.2.3 Device List
      4. 6.2.4 Hardware Platforms and Software Examples
      5. 6.2.5 Documentation
    3. 6.3 Zero CPU Overhead Cyclic Redundancy Check for Embedded On-Chip Memories
      1. 6.3.1 Value Proposition
      2. 6.3.2 In Depth
      3. 6.3.3 Device List
      4. 6.3.4 Hardware Platforms and Software Examples
      5. 6.3.5 Documentation
    4. 6.4 Boot Code Authentication Prior To Code Execution
      1. 6.4.1 Value Proposition
      2. 6.4.2 In Depth
      3. 6.4.3 Device List
      4. 6.4.4 Hardware Platforms and Software Examples
        1. 6.4.4.1 Documentation
  9. 7References
    1. 7.1 Device List
    2. 7.2 Hardware/Software Resources
    3. 7.3 Documentation
  10. 8Revision History

3.2.2 In Depth

There are multiple definitions for division and modulo operations according to the programming language and computer science literature, each of these definitions provide different mathematical properties that can be beneficially employed in the application context. Truncated division is the standard division definition widely used in many programming languages like C. In this definition, the remainder will always have the sign of numerator. The transfer function of truncated division is shown in #GUID-1C361B93-A3E6-4271-9755-F10089434F72 , as can be observed that the function is non-periodic since there is a “platform” around zero point.

GUID-6847BF55-BE35-4432-AE1B-0D3D0B18BDB3-low.gif Figure 3-3 Truncated Division Function

Due to the non-linearity around zero point, the function is not preferred in control applications. Thus non-conventional definitions of division and modulo operations are sometimes preferred for better linearity and periodicity. The transfer function of Floored/Modulo (#GUID-3711F51E-11D5-4BC5-B54C-C55B9B164B17) and Euclidean division (#GUID-21BD91CD-CBC6-4964-8DC5-5E15CA8010EE) functions are shown below. In the modulo division function the remainder will always have the sign of denominator, thus the function is linear around the zero point. In the Euclidean division, the remainder is always positive so the division function is linear around zero point and also the modulo function is periodic.

GUID-85F21690-DDB7-4986-8624-9CCE3ECBB5BC-low.gif Figure 3-4 Floored Division Function
GUID-E3F35F13-8BBD-4D02-835F-96D6DDB38D12-low.gif Figure 3-5 Euclidean Division Function

The C28x CPU has added specialized instructions to enable applications to implement the above division and modulo definitions efficiently in hardware. These new instructions used to enable integer division are interruptible, have very low latency and support different types of operations (ui32/ui32, i32/ui32, i64/i32, ui64/ui32, ui64/ui64, i64/i64, and so forth). The cycles count for the different types of division operations and sizes of the operands achieved using Fast Integer Division unit are listed in and are also compared with the cycles without FID module in Table 3-2. As evident from the table, the FID unit provides several folds improvement in performance for different types of division operations which helps in minimizing the latency of control loop calculations.

Table 3-2 Integer Division With and Without the FID Module
Division Operation Using C Operator '/' Without FASTINTDIV Hardware on C28x Using Intrinsics With FASTINTDIV Hardware + C28x Improvement Factor
i16/i16 traditional 52 16 3.3
i16/i16 Euclidean 56 14 4.0
i16/i16 Modulo 56 14 4.0
u16/u16 56 14 4.0
i32/i32 traditional 59 13 4.5
i32/i32 Euclidean 63 14 4.5
i32/i32 Modulo 63 14 4.5
i32/u32 traditional 37 14 2.6
i32/u32 Modulo 41 14 2.9
u32/u32 37 12 3.1
i32/i16 traditional 60 18 3.3
i32/i16 Euclidean 64 16 4.0
i32/i16 Modulo 64 16 4.0
u32/u16 38 13 2.9
i64/i64 traditional #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 78-2631 42 1.9-62.6
i64/i64 Euclidean #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 82-2635 42 2.0-62.7
i64/i64 Modulo #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 82-2635 42 2.0-62.7
i64/u64 traditional #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 54-2605 42 1.3-62.0
i64/u64 Euclidean #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 58-2609 42 1.4-62.1
i64/u6 Modulo#GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 58-2609 42 1.4-62.1
u64/u64/ #GUID-30F344F4-FCE7-48E2-B3FC-9759AA6E0206 53-2548 42 1.3-60.7
(1) The FASTINTDIV hardware implements 64-bit integer division with optimal fixed number of cycles for fast deterministic behavior. MCUs without such hardware acceleration, implement 64-bit integer division using generic CPU instructions that are not optimized for division or use algorithm techniques that optimize execution based on the value of the numerator and denominator. For instance, if the value of the numerator and denominator is less than 32-bits the software will execute a 32-bit division. Hence, the number of cycles can vary significantly and for large numerator and denominator values, overall cycles are much higher than achievable by the FASTINTDIV accelerator