SPRACN0F October 2021 – March 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
The first step when selecting an MCU for a real-time control system is relatively straightforward process; comparing the components of the MCU to the system needs. There are questions of memory size, CPU speed, communications standards used, analog content, number of I/Os, and so forth. When looking at the fit for an analog module like the ADC, it can appear straightforward to base the decision on sampling rate, number of inputs, and bit level. In practice, however, there is much more to this decision.
Too often ADC selection is based solely on the top level specifications, only to realize during development there are limitations to the system performance due to the ADC itself:
where
An example of how the C2000 ADC is specified and the parameters can be seen in #GUID-C3961371-634F-4011-97EE-A61164A2FE54/T5843526-39, a dynamic link to this same table in the data sheet is located here.
One final aspect of all the parameters that C2000 devices list in the data sheet is what is implied by the inclusion of the parameter itself. For parameters that have a MIN/MAX, these are assured specs over the full operational range and lifetime of the device. The typical (TYP) column is also significant for all parameters, as it represents the mean performance of a parameter across its operational range.
Parameter | Test Conditions | Min | Typ | Max | Unit |
---|---|---|---|---|---|
ADC conversion cycles | 29.6 | 31 | ADCCLKs | ||
Power-up time (after setting ADCPWDNZ to first conversion) | 500 | µs | |||
Gain error | –64 | ±9 | 64 | LSBs | |
Offset error | –16 | ±9 | 16 | LSBs | |
Channel-to-channel gain error | ±6 | LSBs | |||
Channel-to-channel offset error | ±3 | LSBs | |||
ADC-to-ADC gain error | Identical VREFHI and VREFLO for all ADCs | ±6 | LSBs | ||
ADC-to-ADC offset error | Identical VREFHI and VREFLO for all ADCs | ±3 | LSBs | ||
DNL | > –1 | ±0.5 | 1 | LSBs | |
INL | –3 | ±1.5 | 3 | LSBs | |
SNR | VREFHI = 2.5 V, fin = 10 kHz | 87.6 | dB | ||
THD | VREFHI = 2.5 V, fin = 10 kHz | –93.5 | dB | ||
SFDR | VREFHI = 2.5 V, fin = 10 kHz | 95.4 | dB | ||
SINAD | VREFHI = 2.5 V, fin = 10 kHz | 86.6 | dB | ||
ENOB | VREFHI = 2.5 V, fin = 10 kHz, single ADC | 14.1 | bits | ||
VREFHI = 2.5 V, fin = 10 kHz, synchronous ADCs | 14.1 | ||||
VREFHI = 2.5 V, fin = 10 kHz, asynchronous ADCs | Not supported | ||||
PSRR | VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz | 77 | dB | ||
PSRR | VDDA = 3.3-V DC + 200 mV Sine at 800 kHz | 74 | dB | ||
CMRR | DC to 1 MHz | 60 | dB | ||
VREFHI input current | 190 | µA | |||
ADC-to-ADC isolation | VREFHI = 2.5 V, synchronous ADCs | –2 | 2 | LSBs | |
VREFHI = 2.5 V, asynchronous ADCs | Not supported |