SPRACO3 October 2019 INA240 , LMG5200 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S
The block diagram of the system built in BUILD LEVEL 1 is shown in Figure 18. During this step, keep the motor disconnected.
Assuming the load and build steps described in the Section 6.2.2 completed successfully. This section describes the steps for a minimum system check-out, which confirms operation of system interrupt, the peripheral and target independent inverse park transformation, space vector generator modules, and the peripheral dependent PWM initialization and update modules.
NOTE
The tests suggested below for motor 1 by setting 'motorVars[0]' that can be repeated for motor 2 by setting 'motorVars[1]' also to verify the hardware and software integrity in subsequent build levels.