SPRACQ1 May 2020 TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
This section outlines the analog differences between the F2838x and F2837x devices. Most of the Analog modules on F2838x are exactly same as on F2837x. There are some minor enhancements in digital logic of some of the modules that are listed in Table 15.
Module | Feature | F2838x | F2837x |
---|---|---|---|
ADC | Programmable early interrupt | Can be configured via ADCINTCYCLE.OFFSET register | Fixed interrupt time. |
ADC | Post Processing Block Cycle By Cycle Enable | Supported. This feature can be enable by setting ADCPPB1CONFIG.CBCEN register. This feature automatically clears the ADCEVTSTAT on a conversion if the event condition is no longer present. | Not supported |
ADC | 16-bit Single Ended mode | Supported | Not supported |
DAC | No Change | ||
CMPSS | Blanking window | Yes, supported. | No |
CMPSS | RAMPSTS Register | PWMSYNC takes precedence over COMPHSTS when both occur simultaneously. | COMPHSTS takes precedence over PWMSYNC when both occur simultaneously |
CMPSS | LATCHCLR Signal | LATCHCLR signal goes to the sync block, filter and latch | LATCHCLR signal only goes to the latch |
For more details on the Analog module, see the TMS320F2838x Microcontrollers Technical Reference Manual.