SPRACR6 April   2020 F29H850TU , F29H859TU-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Distributed Power Control Architecture With Multiple MCUs Over FSI
    1.     Trademarks
    2. 1 Introduction
    3. 2 Distributed Power Control Architecture
      1. 2.1 Distributed Power Control Architecture – DC/AC System
      2. 2.2 Distributed Power Control Architecture – AC/DC System
      3. 2.3 Distributed Power Control Architecture – DC/DC System
    4. 3 DC/AC System - Power Topologies
      1. 3.1 MPPT DC/DC Stage
      2. 3.2 DC/AC Inverter Stage
    5. 4 C2000 Controller Configuration for DPCA DC/AC System
    6. 5 Communication Interface – FSI for DPCA DC/AC System
      1. 5.1 FSI Star Connection
      2. 5.2 FSI Daisy Chain Connection
      3. 5.3 FSI Frame
      4. 5.4 FSI Transmission Latencies
    7. 6 Summary
    8. 7 References

5.3 FSI Frame

The FSI module transmits and receives information in frames. The shortest frame is 16 bits long (without counting the preamble and post amble clock edges). The basic frame structure for 16-bit data is shown in Table 2. Table 3 shows the same for 128-bit data. In the normal mode of transmission, there are four preamble clock edges before the start of the frame and 4 clock edges after the frame. Data is transmitted on both edges of the clock. Each field of the frame (like the Start-of-Frame, Frame type, and so forth) will be transmitted with the most significant bit sent first.

Table 2. Data Frame With 1 Word (16-bits) of Data

IDLE State Preamble Start of Frame Frame Type User Defined Data Data Words CRC Byte Frame Tag End of Frame Post Frame Clocks IDLE
4 clock edges 1001 0100 8 bits 16 bits 8 bits 4 bits 0110 4 clock edges

Table 3. Data Frame With 1 Word (16-bits) of Data

IDLE State Preamble Start of Frame Frame Type User Defined Data Data Words CRC Byte Frame Tag End of Frame Post Frame Clocks IDLE
4 clock edges 1001 0100 8 bits 128 bits 8 bits 4 bits 0110 4 clock edges