SPRACX6 June   2021 DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Firewall Documentation
    1. 2.1 Technical Reference Manual (TRM)
    2. 2.2 SDK TISCI Documentation
    3. 2.3 SDK Firewall Documentation
    4. 2.4 TI NDA Firewall Slide Sets
  4. 3Firewall Definitions and Terms
  5. 4SysConfig Tool
  6. 5Master Firewall versus Slave Firewall
    1. 5.1 Slave Firewalls
    2. 5.2 Master Firewalls
    3. 5.3 A72 Master Firewall
  7. 6Where to Firewall
    1. 6.1 Example
  8. 7Programming Firewalls
    1. 7.1 Sample SBL Code
      1. 7.1.1 Create a Table
      2. 7.1.2 Parse the Table of Firewall Regions
      3. 7.1.3 Utility Functions
      4. 7.1.4 Processor SDK 7.1 SBL Example

6 Where to Firewall

What DDR memory ranges to firewall will differ from customer to customer, and from use case to use case. Taking a default TI SDK release as an example, some easy first steps can be seen.

Each release of the PSDK, when built for vision_apps solutions, will generate a system memory map. The system memory map shows memory that is specific to each, core, and memory that shared between cores. This memory map is a recommended resource for determining which areas should be firewalled for A72 access.