SPRACX6 June 2021 DRA821U , DRA821U , DRA821U-Q1 , DRA821U-Q1 , DRA829J , DRA829J , DRA829J-Q1 , DRA829J-Q1 , DRA829V , DRA829V , DRA829V-Q1 , DRA829V-Q1 , TDA4VM , TDA4VM , TDA4VM-Q1 , TDA4VM-Q1
Create a table with entries in which each entry represents a firewall region. This format is the same format as the .c output used by SysConfig tool. In the example below, three regions are created for the A72 Master firewall.
struct ti_sci_msg_fwl_region {
uint16_t fwl_id;
uint16_t region;
uint32_t n_permission_regs;
uint32_t control;
uint32_t permissions[FWL_MAX_PRIVID_SLOTS];
uint64_t start_address;
uint64_t end_address;
} __attribute__((__packed__));
void J721E_Set_Firewall(uint32_t isBuildHs)
{
int32_t status = CSL_EFAIL;
struct ti_sci_msg_fwl_region j721e_fwl_data[] = {
/* compute_cluster Master firewall - background region 0 */
{
.fwl_id = CSL_MSTR_FW_A72SS0_CORE0_CPU_0_CPU_0_MSMC_ID,
.region = 0,
.n_permission_regs = 1,
.control = 0x30A,
.start_address = 0x00000000,
.end_address = 0xFFFFFFFFF,
.permissions = { 0x1FFFF }, // PrivId 1U
},
/* compute_cluster Master firewall - region 1 */
{
.fwl_id = CSL_MSTR_FW_A72SS0_CORE0_CPU_0_CPU_0_MSMC_ID,
.region = 1,
.n_permission_regs = 1,
.control = 0x20A,
.start_address = 0xa0000000,
.end_address = 0xa8ffffff,
.permissions = { 0x10000 }, // PrivId 1U
},
/* compute_cluster Master firewall - region 2 */
{
.fwl_id = CSL_MSTR_FW_A72SS0_CORE0_CPU_0_CPU_0_MSMC_ID,
.region = 2,
.n_permission_regs = 1,
.control = 0x20A,
.start_address = 0xce000000,
.end_address = 0xfbffffff,
.permissions = { 0x10000 }, // PrivId 1U
},
};