SPRACY3 June   2021 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040C-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280048C-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28076 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Design Overview
  4. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
    4. 3.4 Completed Design
  5. 4Normal Operation With CBC Protection Configuration
    1. 4.1 CBC Protection Configuration
    2. 4.2 Swapping EPWM Configurations During Zero Cross Point
  6. 5Other Considerations
    1. 5.1 Trip Sourced From CMPSS
    2. 5.2 Extend to 3 Phase Inverter
      1. 5.2.1 Input Selection
      2. 5.2.2 Output Selection
    3. 5.3 Achieve 2 Level Protection Scheme
  7. 6Test Results
  8. 7References

5.2.1 Input Selection

At the beginning, GPIO8 and GPIO9 are configured as EPWM5A and EPWM5B, while GPIO10 and GPIO11 are configured as EPWM6A and EPWM6B, respectively. Secondly, use Input X-BAR to select the related GPIO pins for EPWM5B and EPWM6B.

XBAR_setInputPin(XBAR_INPUT3,9);        // INPUT X-BAR 3 = GPIO9 = EPWM5B
XBAR_setInputPin(XBAR_INPUT4,11);       // INPUT X-BAR 4 = GPIO11 = EPWM6B

Then, use CLB X-BAR to select the INPUT X-BAR INPUT 3 and INPUT4 as AUXSIG1 and AUXSIG2. In this example, CLB Tile 1 can be also used to handle the delayed protection for EPWM5B and EPWM6B, together with EPWM1B.

    //for EPWM5B/EPWM6B input to CLB
    XBAR_setCLBMuxConfig(XBAR_AUXSIG1, XBAR_CLB_MUX05_INPUTXBAR3);
    XBAR_enableCLBMux(XBAR_AUXSIG1, XBAR_MUX05);
    XBAR_setCLBMuxConfig(XBAR_AUXSIG2, XBAR_CLB_MUX07_INPUTXBAR4);
    XBAR_enableCLBMux(XBAR_AUXSIG2, XBAR_MUX07);

    CLB_configLocalInputMux(CLB1_BASE, CLB_IN3, CLB_LOCAL_IN_MUX_GLOBAL_IN);
    CLB_configLocalInputMux(CLB1_BASE, CLB_IN4, CLB_LOCAL_IN_MUX_GLOBAL_IN);

    CLB_configGlobalInputMux(CLB1_BASE, CLB_IN3, CLB_GLOBAL_IN_MUX_CLB_AUXSIG1);
    CLB_configGlobalInputMux(CLB1_BASE, CLB_IN4, CLB_GLOBAL_IN_MUX_CLB_AUXSIG2);

    CLB_configGPInputMux(CLB1_BASE, CLB_IN3, CLB_GP_IN_MUX_EXTERNAL);
    CLB_configGPInputMux(CLB1_BASE, CLB_IN4, CLB_GP_IN_MUX_EXTERNAL);