SPRACY3 June   2021 F29H850TU , F29H859TU-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040C-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280048C-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28076 , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Design Overview
  4. 3CLB Implementation
    1. 3.1 CLB Input Selection
    2. 3.2 Counter and FSM Configuration
    3. 3.3 CLB Output
    4. 3.4 Completed Design
  5. 4Normal Operation With CBC Protection Configuration
    1. 4.1 CBC Protection Configuration
    2. 4.2 Swapping EPWM Configurations During Zero Cross Point
  6. 5Other Considerations
    1. 5.1 Trip Sourced From CMPSS
    2. 5.2 Extend to 3 Phase Inverter
      1. 5.2.1 Input Selection
      2. 5.2.2 Output Selection
    3. 5.3 Achieve 2 Level Protection Scheme
  7. 6Test Results
  8. 7References

3.3 CLB Output

The final step is to use the output LUT block to combine the FSM_OUT and original EPWM1B’ with AND logic. According to the Table 3-2, OUTPUT LUT2_0 of CLB TILE1 is used to route the resulting output (FSM_OUT&EPWM1B’) as the new EPWM1B, as shown in Figure 3-4. Likewise, OUTPUT LUT2_0 of CLB TILE2 is used for EPWM2B. That is why two CLB TILEs are required in this application.

Table 3-2 Peripheral Signal Multiplexer Table
CLB Instance CLB Output Signal Peripheral Signal Peripheral Name
CBL1 CLB1_OUT0_0 PWMA EPWM1
CBL1 CLB1_OUT1_0 PWMA_OE EPWM1
CBL1 CLB1_OUT2_0 PWMB EPWM1
CBL1 CLB1_OUT3_0 PWMB_OE EPWM1
CBL1 CLB1_OUT4_0 AQ_PWMA EPWM1
CBL1 CLB1_OUT5_0 AQ_PWMB EPWM1
CBL1 CLB1_OUT6_0 DB_PWMA EPWM1
CBL1 CLB1_OUT7_0 DB_PWMB EPWM1
CBL1 CLB1_OUT0_1 QA EQEP1
CBL1 CLB1_OUT1_1 QB EQEP1
CBL1 CLB1_OUT2_1 DDIR EQEP1
CBL1 CLB1_OUT3_1 QCLK EQEP1
CBL1 CLB1_OUT4_1 G1.2 CLB X BAR
CBL1 CLB1_OUT5_1 G3.2 CLB X BAR
GUID-20210428-CA0I-40Z1-HCTN-GH3WW39B2R83-low.png Figure 3-4 OUTPUT LUT2_0 Configuration

As shown in Table 3-2, each CLB output signal passes through an external multiplexer that intersects a specific peripheral signal. Thus, to export the CLB output to the original EPWM1B pin (GPIO1 in the example), it is needed to enable the OUTPUT LUT2_0 using the OUT_EN register, as shown in the below code snippets.

CLB_setOutputMask(CLB1_BASE, 0x4, true);   //1<<2 out2

CLB_setOutputMask(CLB2_BASE, 0x4, true);  //1<<2 out2