SPRACZ5 December   2021 DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Enabling Thermal Shutdown Mandatory Step
  4. 3Thermal Mitigation Strategies at a High Level
    1. 3.1 Strategy 1: Auditing the Power Domains That Contribute to the Highest Power Consumption
    2. 3.2 Strategy 2: Disable Loading of Remote Core Firmware
    3. 3.3 Strategy 3: Disabling Modules on TDA4
      1. 3.3.1 Example: Disabling PCIe Instances on 7.3
    4. 3.4 Strategy 4: Dynamic Frequency Scaling (DFS)
    5. 3.5 Strategy 5: How to Reduce Frequency of Other Cores
  5. 4References

3.5 Strategy 5: How to Reduce Frequency of Other Cores

To set the C7x clock frequency to 500 MHz, device ID for C7x = 16 and CLK_ID = 1 use the following command on the Linux command line:

root@j7-evm:~# k3conf set clock 16 1 500000000

|----------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|----------------------------------------------------------------------------------------|
| 16 | 0 | DEV_C71SS0_MMA_PLL_CTRL_CLK | CLK_STATE_READY | 500000000 |
| 16 | 1 | DEV_C71SS0_MMA_MMA_CLK | CLK_STATE_READY | 500000000 |

To reduce the R5F clock frequency from 1GHZ to 500 MHz, device ID for MAIN_R5FSS0_CORE0 = 245 and CLK_ID = 0 use the following command on the Linux command line:

root@j7-evm:~# k3conf set clock 245 0 500000000
|---------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|---------------------------------------------------------------------------------------------|
| 245 | 0 | DEV_R5FSS0_CORE0_CPU_CLK | CLK_STATE_READY | 500000000 |
| 245 | 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | CLK_STATE_READY | 500000000 |
| 245 | 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | CLK_STATE_READY | 500000000 |