SPRAD00 December   2021 DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM

 

  1.   Trademarks
  2. 1Introduction
  3. 2Jacinto 7 Display Subsystem Overview
    1. 2.1 Video (Input) Pipelines
    2. 2.2 Writeback Pipeline
    3. 2.3 Overlay Manager
    4. 2.4 Output Processing
    5. 2.5 Output Display Interfaces
      1. 2.5.1 Embedded Display Port (eDP)
      2. 2.5.2 MIPI Display Serial Interface (DSI)
      3. 2.5.3 Display Parallel Interface (DPI)
    6. 2.6 Safety Support
  4. 3Display Subsystem Use-case Examples
    1. 3.1 3-Display Configuration
  5. 4TDA4VM/DRA829V Hardware Display Support
  6. 5 Display Subsystem Software Architecture
    1. 5.1 Linux DSS Architecture
    2. 5.2 QNX Software Architecture
    3. 5.3 RTOS-Based DSS Support
  7. 6References

2.5.1 Embedded Display Port (eDP)

  • Compliance with VESA Display Port (DP) 1.3 (with 1.4 DSC/FEC support) specification
  • Compliance with VESA embedded Display Port (eDP) 1.4 specification
  • Static configuration of either DP or eDP mode
  • Single Stream Transport (SST)
  • Multiple Stream Transport (MST)
    • Up to 4 video and up to 1 audio sources
    • Support for up to 25 GBps throughput (equivalent to approximately 4K + 2xFHD streams) use case
  • The DP (Physical Layer) SERDES and Aux PHY modules support
    • DP1.3 HBR3 and eDP1.4a HBR3 throughput
    • 1, 2, or 4 lanes at 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps per lane
    • Hot Plug Detect (HPD) for connection detection and interrupt from sink