SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

6 Revision History

Changes from February 1, 2023 to December 13, 2023 (from Revision (February 2023) to Revision A (December 2023))

  • Added AM62Px device throughout the document.Go
  • Updated the numbering format for tables, figures and cross-references throughout the document.Go
  • Updates were made in Section 1.4.1,Go
  • Reordered rows and added 2 Channel, 2 Die, 2 Rank row in Table 2-1.Go
  • Added 10k pull-down to RESET_n in each figure, RESET_n has no length matching requirement, removed ODT_CA_B and fixed missing connection to DQ[7:0] in Figure 2-3.Go
  • Update was made in Section 2.12.Go
  • Relaxed skew limits, skew considers SOC package delays (see appendix) and PCB delays, simulation must be performed to check delays and skew, clarified and reordered notes in Table 2-6.Go
  • Relaxed skew limits, skew considers SOC package delays (see appendix) and PCB delays, simulation must be performed to check delays and skew, clarified and reordered notes in Table 2-7.Go
  • Updates were made in Section 3.3.Go
  • Updates were made in Section 3.5.Go
  • Removed Waveform Quality section (ring-back margins).Go
  • Update was made in Section 3.5.3.1.Go
  • LPDDR4-3733 Read eye mask VdlVW corrected to 140mV in Table 3-3.Go
  • Added AM62Px SK EVM stackup into Table 3-6 .Go
  • Corrected Impedance Mismatch calculation in Table 3-11.Go
  • Removed Minimum ring-back margins at high/low levels (JEDEC)Go
  • Added Section 4 Go