To avoid sub-harmonics oscillation, slope compensation is required to induced for the inner current loop [1]. For C2000 devices, each CMPSS provides the ramp generator dedicated for slope compensation. As shown in Figure 3-1, the ramp generator produces a falling ramp waveform for the high-reference 12-bit DAC as the negative input of CMPSS. The calculated value from voltage control loop compensator is used to decide the initial value of the ramp register RAMPSTS. After receiving the selected ramp source signal (EPWM1SYNCE in this case), the defined slope value, is subtracted from RAMPSTS on every subsequent CPU cycle. In addition, to filter out the unexpected noise at the VCR signal, the suggestion is to enable the digital filter, which is helpful to avoid the unexpected comparator actions by switching noise. The recommendation is to select the latch output option of CMPSS for the further PWM control, since the latch feature ensures only the 1^st comparator event can take effect, regardless of any further events within the same switching cycle. The latched output status of CMPSS is required to be cleared by the same EPWMxSYNCPER signal, to monitor the VCR signal in the new switching cycle.

Figure 3-1 CMPSS Block Diagram