SPRUHM8K December   2013  – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II)
  5. 3 System Control and Interrupt
    1. 3.1  Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Power-On Reset (POR)
      4. 3.3.4  Debugger Reset (SYSRS)
      5. 3.3.5  Watchdog Reset (WDRS)
      6. 3.3.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.3.7  DCSM Safe Code Copy Reset (SCCRESET)
      8. 3.3.8  Hibernate Reset (HIBRESET)
      9. 3.3.9  Hardware BIST Reset (HWBISTRS)
      10. 3.3.10 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
        4. 3.4.2.4 Dual-CPU Interrupt Handling
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable ECC Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
        4. 3.5.3.4 NMI Vector Fetch Mismatch
        5. 3.5.3.5 CPU2 Watchdog or NMI Watchdog Reset
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 Missing Clock Detection Logic
      3. 3.6.3 PLLSLIP Detection
      4. 3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check
      5. 3.6.5 NMIWDs
      6. 3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
      7. 3.6.7 ECC Enabled Flash Memory
      8. 3.6.8 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 XCLKOUT
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Clock Source and PLL Setup
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 Clock Configuration Examples
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timers
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 IDLE
      2. 3.10.2 STANDBY
      3. 3.10.3 HALT
      4. 3.10.4 Hibernate (HIB)
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1  Dedicated RAM (Dx RAM)
        2. 3.11.1.2  Local Shared RAM (LSx RAM)
        3. 3.11.1.3  Global Shared RAM (GSx RAM)
        4. 3.11.1.4  CPU Message RAM (CPU MSG RAM)
        5. 3.11.1.5  CLA Message RAM (CLA MSGRAM)
        6. 3.11.1.6  Access Arbitration
        7. 3.11.1.7  Access Protection
          1. 3.11.1.7.1 CPU Fetch Protection
          2. 3.11.1.7.2 CPU Write Protection
          3. 3.11.1.7.3 CPU Read Protection
          4. 3.11.1.7.4 CLA Fetch Protection
          5. 3.11.1.7.5 CLA Write Protection
          6. 3.11.1.7.6 CLA Read Protection
          7. 3.11.1.7.7 DMA Write Protection
        8. 3.11.1.8  Memory Error Detection, Correction and Error Handling
          1. 3.11.1.8.1 Error Detection and Correction
          2. 3.11.1.8.2 Error Handling
        9. 3.11.1.9  Application Test Hooks for Error Detection and Correction
        10. 3.11.1.10 RAM Initialization
    12. 3.12 Flash and OTP Memory
      1. 3.12.1  Features
      2. 3.12.2  Flash Tools
      3. 3.12.3  Default Flash Configuration
      4. 3.12.4  Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
      5. 3.12.5  Flash Module Controller (FMC)
      6. 3.12.6  Flash and OTP Memory Power-Down Modes and Wakeup
      7. 3.12.7  Flash and OTP Memory Performance
      8. 3.12.8  Flash Read Interface
        1. 3.12.8.1 FMC Flash Read Interface
          1. 3.12.8.1.1 Standard Read Mode
          2. 3.12.8.1.2 Prefetch Mode
            1. 3.12.8.1.2.1 Data Cache
      9. 3.12.9  Erase/Program Flash
        1. 3.12.9.1 Erase
        2. 3.12.9.2 Program
        3. 3.12.9.3 Verify
      10. 3.12.10 Error Correction Code (ECC) Protection
        1. 3.12.10.1 Single-Bit Data Error
        2. 3.12.10.2 Uncorrectable Error
        3. 3.12.10.3 SECDED Logic Correctness Check
        4. 3.12.10.4 Reading ECC Memory From a Higher Address Space
      11. 3.12.11 Reserved Locations Within Flash and OTP Memory
      12. 3.12.12 Procedure to Change the Flash Control Registers
      13. 3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
      14. 3.12.14 Flash Pump Ownership Semaphore
        1. 3.12.14.1 Clock Configuration Semaphore
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 Emulation Code Security Logic (ECSL)
        2. 3.13.1.2 CPU Secure Logic
        3. 3.13.1.3 Execute-Only Protection
        4. 3.13.1.4 Password Lock
        5. 3.13.1.5 JTAG Lock
        6. 3.13.1.6 Link Pointer and Zone Select
          1. 3.13.1.6.1 C Code Example to get Zone Select Block Addr for Zone1
        7. 3.13.1.7 Flash and OTP Memory Erase/Program
        8. 3.13.1.8 Safe Copy Code
        9. 3.13.1.9 SafeCRC
      2. 3.13.2 CSM Impact on Other On-Chip Resources
      3. 3.13.3 Incorporating Code Security in User Applications
        1. 3.13.3.1 Environments That Require Security Unlocking
        2. 3.13.3.2 CSM Password Match Flow
        3. 3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
          1. 3.13.3.3.1 C Code Example to Unsecure C28x Zone1
          2. 3.13.3.3.2 C Code Example to Resecure C28x Zone1
        4. 3.13.3.4 Environments That Require ECSL Unlocking
        5. 3.13.3.5 ECSL Password Match Flow
        6. 3.13.3.6 ECSL Disable Considerations for any Zone
          1. 3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
        7. 3.13.3.7 Device Unique ID
    14. 3.14 JTAG
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 Software
      1. 3.16.1 SYSCTL Examples
        1. 3.16.1.1 Missing clock detection (MCD)
        2. 3.16.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.16.2 TIMER Examples
        1. 3.16.2.1 CPU Timers
        2. 3.16.2.2 CPU Timers
      3. 3.16.3 MEMCFG Examples
      4. 3.16.4 INTERRUPT Examples
        1. 3.16.4.1 External Interrupts (ExternalInterrupt)
        2. 3.16.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.16.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.16.4.4 EPWM Real-Time Interrupt
      5. 3.16.5 LPM Examples
      6. 3.16.6 WATCHDOG Examples
        1. 3.16.6.1 Watchdog
    17. 3.17 System Control Registers
      1. 3.17.1  System Control Base Addresses
      2. 3.17.2  CPUTIMER_REGS Registers
      3. 3.17.3  PIE_CTRL_REGS Registers
      4. 3.17.4  WD_REGS Registers
      5. 3.17.5  NMI_INTRUPT_REGS Registers
      6. 3.17.6  XINT_REGS Registers
      7. 3.17.7  SYNC_SOC_REGS Registers
      8. 3.17.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.17.9  FLASH_PUMP_SEMAPHORE_REGS Registers
      10. 3.17.10 DEV_CFG_REGS Registers
      11. 3.17.11 CLK_CFG_REGS Registers
      12. 3.17.12 CPU_SYS_REGS Registers
      13. 3.17.13 ROM_PREFETCH_REGS Registers
      14. 3.17.14 DCSM_Z1_REGS Registers
      15. 3.17.15 DCSM_Z2_REGS Registers
      16. 3.17.16 DCSM_COMMON_REGS Registers
      17. 3.17.17 MEM_CFG_REGS Registers
      18. 3.17.18 ACCESS_PROTECTION_REGS Registers
      19. 3.17.19 MEMORY_ERROR_REGS Registers
      20. 3.17.20 ROM_WAIT_STATE_REGS Registers
      21. 3.17.21 FLASH_CTRL_REGS Registers
      22. 3.17.22 FLASH_ECC_REGS Registers
      23. 3.17.23 CPU_ID_REGS Registers
      24. 3.17.24 UID_REGS Registers
      25. 3.17.25 DCSM_Z1_OTP Registers
      26. 3.17.26 DCSM_Z2_OTP Registers
      27. 3.17.27 Register to Driverlib Function Mapping
        1. 3.17.27.1 CPUTIMER Registers to Driverlib Functions
        2. 3.17.27.2 ASYSCTL Registers to Driverlib Functions
        3. 3.17.27.3 PIE Registers to Driverlib Functions
        4. 3.17.27.4 SYSCTL Registers to Driverlib Functions
        5. 3.17.27.5 NMI Registers to Driverlib Functions
        6. 3.17.27.6 XINT Registers to Driverlib Functions
        7. 3.17.27.7 DCSM Registers to Driverlib Functions
        8. 3.17.27.8 MEMCFG Registers to Driverlib Functions
        9. 3.17.27.9 FLASH Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  Boot ROM Registers
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
    5. 4.5  Configuring Boot Mode Pins
    6. 4.6  Configuring Get Boot Options
    7. 4.7  Configuring Emulation Boot Options
    8. 4.8  Device Boot Flow Diagrams
      1. 4.8.1 Emulation Boot Flow Diagrams
      2. 4.8.2 Standalone and Hibernate Boot Flow Diagrams
    9. 4.9  Device Reset and Exception Handling
      1. 4.9.1 Reset Causes and Handling
      2. 4.9.2 Exceptions and Interrupts Handling
    10. 4.10 Boot ROM Description
      1. 4.10.1  Entry Points
      2. 4.10.2  Wait Points
      3. 4.10.3  Memory Maps
        1. 4.10.3.1 CPU1 Boot ROM Memory Map
        2. 4.10.3.2 CPU2 Boot ROM Memory Map
        3. 4.10.3.3 CLA Data ROM Memory Map
        4. 4.10.3.4 Reserved RAM and Flash Memory-Map
        5. 4.10.3.5 ROM Tables
          1. 4.10.3.5.1 Boot ROM Tables
          2. 4.10.3.5.2 CLA ROM Tables
      4. 4.10.4  Boot Modes
        1. 4.10.4.1 Wait Boot Mode
        2. 4.10.4.2 SCI Boot Mode
        3. 4.10.4.3 SPI Boot Mode
        4. 4.10.4.4 I2C Boot Mode
        5. 4.10.4.5 Parallel Boot Mode
        6. 4.10.4.6 CAN Boot Mode
        7. 4.10.4.7 USB Boot Mode
      5. 4.10.5  Boot Data Stream Structure
        1. 4.10.5.1 Bootloader Data Stream Structure
          1. 4.10.5.1.1 Data Stream Structure 8-bit
      6. 4.10.6  GPIO Assignments
      7. 4.10.7  Secure ROM Function APIs
      8. 4.10.8  Boot IPC
        1. 4.10.8.1 CPU1 IPC Commands
        2. 4.10.8.2 CPU2 IPC Commands
        3. 4.10.8.3 CPU2 IPC Error Commands
      9. 4.10.9  Clock Initializations
      10. 4.10.10 Wait State Configuration
      11. 4.10.11 Boot Status information
        1. 4.10.11.1 CPU1 Booting Status
        2. 4.10.11.2 CPU1 Boot Mode Status
        3. 4.10.11.3 CPU2 Booting Status
        4. 4.10.11.4 CPU1 IPC NAK Status
        5. 4.10.11.5 CPU2 IPC NAK Status
      12. 4.10.12 ROM Version
  7. 5 Direct Memory Access (DMA)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
    2. 5.2 Architecture
      1. 5.2.1 Common Peripheral Architecture
      2. 5.2.2 Peripheral Interrupt Event Trigger Sources
      3. 5.2.3 DMA Bus
    3. 5.3 Address Pointer and Transfer Control
    4. 5.4 Pipeline Timing and Throughput
    5. 5.5 CPU and CLA Arbitration
    6. 5.6 Channel Priority
      1. 5.6.1 Round-Robin Mode
      2. 5.6.2 Channel 1 High-Priority Mode
    7. 5.7 Overrun Detection Feature
    8. 5.8 Software
      1. 5.8.1 DMA Examples
        1. 5.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 5.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 5.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 5.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 5.9 DMA Registers
      1. 5.9.1 DMA Base Addresses
      2. 5.9.2 DMA_REGS Registers
      3. 5.9.3 DMA_CH_REGS Registers
      4. 5.9.4 DMA Registers to Driverlib Functions
  8. 6 Control Law Accelerator (CLA)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 CLA Related Collateral
      3. 6.1.3 Block Diagram
    2. 6.2 CLA Interface
      1. 6.2.1 CLA Memory
      2. 6.2.2 CLA Memory Bus
      3. 6.2.3 Shared Peripherals and EALLOW Protection
      4. 6.2.4 CLA Tasks and Interrupt Vectors
      5. 6.2.5 CLA Software Interrupt to CPU
    3. 6.3 CLA and CPU Arbitration
      1. 6.3.1 CLA Message RAM
      2. 6.3.2 CLA Program Memory
      3. 6.3.3 CLA Data Memory
      4. 6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 6.4 CLA Configuration and Debug
      1. 6.4.1 Building a CLA Application
      2. 6.4.2 Typical CLA Initialization Sequence
      3. 6.4.3 Debugging CLA Code
        1. 6.4.3.1 Breakpoint Support (MDEBUGSTOP)
      4. 6.4.4 CLA Illegal Opcode Behavior
      5. 6.4.5 Resetting the CLA
    5. 6.5 Pipeline
      1. 6.5.1 Pipeline Overview
      2. 6.5.2 CLA Pipeline Alignment
        1. 6.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       350
        3. 6.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       352
        5. 6.5.2.3 ADC Early Interrupt to CLA Response
      3. 6.5.3 Parallel Instructions
        1. 6.5.3.1 Math Operation with Parallel Load
        2. 6.5.3.2 Multiply with Parallel Add
      4. 6.5.4 CLA Task Execution Latency
    6. 6.6 Software
      1. 6.6.1 CLA Examples
        1. 6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
    7. 6.7 Instruction Set
      1. 6.7.1 Instruction Descriptions
      2. 6.7.2 Addressing Modes and Encoding
      3. 6.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest {, CNDF}
        11.       MCCNDD 16BitDest {, CNDF}
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 {, CNDF}
        45.       MMOV32 MRa, MRb {, CNDF}
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb{, CNDF}
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD {CNDF}
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb {, CNDF}
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 6.8 CLA Registers
      1. 6.8.1 CLA Base Addresses
      2. 6.8.2 CLA_REGS Registers
      3. 6.8.3 CLA_SOFTINT_REGS Registers
      4. 6.8.4 CLA Registers to Driverlib Functions
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Introduction
    2. 7.2 Message RAMs
    3. 7.3 IPC Flags and Interrupts
    4. 7.4 IPC Command Registers
    5. 7.5 Free-Running Counter
    6. 7.6 IPC Communication Protocol
    7. 7.7 IPC Registers
      1. 7.7.1 IPC Base Addresses
      2. 7.7.2 IPC_REGS_CPU1 Registers
      3. 7.7.3 IPC_REGS_CPU2 Registers
      4. 7.7.4 IPC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1  Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2  Configuration Overview
    3. 8.3  Digital General-Purpose I/O Control
    4. 8.4  Input Qualification
      1. 8.4.1 No Synchronization (Asynchronous Input)
      2. 8.4.2 Synchronization to SYSCLKOUT Only
      3. 8.4.3 Qualification Using a Sampling Window
    5. 8.5  USB Signals
    6. 8.6  SPI Signals
    7. 8.7  GPIO and Peripheral Muxing
      1. 8.7.1 GPIO Muxing
      2. 8.7.2 Peripheral Muxing
    8. 8.8  Internal Pullup Configuration Requirements
    9. 8.9  Software
      1. 8.9.1 GPIO Examples
        1. 8.9.1.1 Device GPIO Setup
        2. 8.9.1.2 Device GPIO Toggle
        3. 8.9.1.3 Device GPIO Interrupt
      2. 8.9.2 LED Examples
    10. 8.10 GPIO Registers
      1. 8.10.1 GPIO Base Addresses
      2. 8.10.2 GPIO_CTRL_REGS Registers
      3. 8.10.3 GPIO_DATA_REGS Registers
      4. 8.10.4 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR
    2. 9.2 ePWM, CLB, and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 CLB X-BAR
        1. 9.2.2.1 CLB X-BAR Architecture
      3. 9.2.3 GPIO Output X-BAR
        1. 9.2.3.1 GPIO Output X-BAR Architecture
      4. 9.2.4 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Addresses
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 CLB_XBAR_REGS Registers
      6. 9.3.6 OUTPUT_XBAR_REGS Registers
      7. 9.3.7 Register to Driverlib Function Mapping
        1. 9.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.7.2 XBAR Registers to Driverlib Functions
        3. 9.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 9.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  12. 10Analog Subsystem
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Optimizing Power-Up Time
    3. 10.3 Analog Subsystem Registers
      1. 10.3.1 Analog Subsystem Base Addresses
      2. 10.3.2 ANALOG_SUBSYS_REGS Registers
  13. 11Analog-to-Digital Converter (ADC)
    1. 11.1  Introduction
      1. 11.1.1 ADC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2  ADC Configurability
      1. 11.2.1 Clock Configuration
      2. 11.2.2 Resolution
      3. 11.2.3 Voltage Reference
        1. 11.2.3.1 External Reference Mode
      4. 11.2.4 Signal Mode
      5. 11.2.5 Expected Conversion Results
      6. 11.2.6 Interpreting Conversion Results
    3. 11.3  SOC Principle of Operation
      1. 11.3.1 SOC Configuration
      2. 11.3.2 Trigger Operation
      3. 11.3.3 ADC Acquisition (Sample and Hold) Window
      4. 11.3.4 ADC Input Models
      5. 11.3.5 Channel Selection
    4. 11.4  SOC Configuration Examples
      1. 11.4.1 Single Conversion from ePWM Trigger
      2. 11.4.2 Oversampled Conversion from ePWM Trigger
      3. 11.4.3 Multiple Conversions from CPU Timer Trigger
      4. 11.4.4 Software Triggering of SOCs
    5. 11.5  ADC Conversion Priority
    6. 11.6  Burst Mode
      1. 11.6.1 Burst Mode Example
      2. 11.6.2 Burst Mode Priority Example
    7. 11.7  EOC and Interrupt Operation
      1. 11.7.1 Interrupt Overflow
      2. 11.7.2 Continue to Interrupt Mode
      3. 11.7.3 Early Interrupt Configuration Mode
    8. 11.8  Post-Processing Blocks
      1. 11.8.1 PPB Offset Correction
      2. 11.8.2 PPB Error Calculation
      3. 11.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 11.8.4 PPB Sample Delay Capture
    9. 11.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 11.9.1 Implementation
      2. 11.9.2 Detecting an Open Input Pin
      3. 11.9.3 Detecting a Shorted Input Pin
    10. 11.10 Power-Up Sequence
    11. 11.11 ADC Calibration
      1. 11.11.1 ADC Zero Offset Calibration
      2. 11.11.2 ADC Calibration Routines in OTP Memory
    12. 11.12 ADC Timings
      1. 11.12.1 ADC Timing Diagrams
    13. 11.13 Additional Information
      1. 11.13.1 Ensuring Synchronous Operation
        1. 11.13.1.1 Basic Synchronous Operation
        2. 11.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 11.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 11.13.1.4 Synchronous Operation with Different Resolutions
        5. 11.13.1.5 Non-overlapping Conversions
      2. 11.13.2 Choosing an Acquisition Window Duration
      3. 11.13.3 Achieving Simultaneous Sampling
      4. 11.13.4 Result Register Mapping
      5. 11.13.5 Internal Temperature Sensor
      6. 11.13.6 Designing an External Reference Circuit
    14. 11.14 Software
      1. 11.14.1 ADC Examples
        1. 11.14.1.1  ADC Software Triggering
        2. 11.14.1.2  ADC ePWM Triggering
        3. 11.14.1.3  ADC Temperature Sensor Conversion
        4. 11.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 11.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 11.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 11.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 11.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 11.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 11.14.1.10 ADC Burst Mode
        11. 11.14.1.11 ADC Burst Mode Oversampling
        12. 11.14.1.12 ADC SOC Oversampling
        13. 11.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
    15. 11.15 ADC Registers
      1. 11.15.1 ADC Base Addresses
      2. 11.15.2 ADC_RESULT_REGS Registers
      3. 11.15.3 ADC_REGS Registers
      4. 11.15.4 ADC Registers to Driverlib Functions
  14. 12Buffered Digital-to-Analog Converter (DAC)
    1. 12.1 Introduction
      1. 12.1.1 DAC Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Block Diagram
    2. 12.2 Using the DAC
      1. 12.2.1 Initialization Sequence
      2. 12.2.2 DAC Offset Adjustment
      3. 12.2.3 EPWMSYNCPER Signal
    3. 12.3 Lock Registers
    4. 12.4 Software
      1. 12.4.1 DAC Examples
        1. 12.4.1.1 Buffered DAC Enable
        2. 12.4.1.2 Buffered DAC Random
        3. 12.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 12.5 DAC Registers
      1. 12.5.1 DAC Base Addresses
      2. 12.5.2 DAC_REGS Registers
      3. 12.5.3 DAC Registers to Driverlib Functions
  15. 13Comparator Subsystem (CMPSS)
    1. 13.1 Introduction
      1. 13.1.1 CMPSS Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2 Comparator
    3. 13.3 Reference DAC
    4. 13.4 Ramp Generator
      1. 13.4.1 Ramp Generator Overview
      2. 13.4.2 Ramp Generator Behavior
      3. 13.4.3 Ramp Generator Behavior at Corner Cases
    5. 13.5 Digital Filter
      1. 13.5.1 Filter Initialization Sequence
    6. 13.6 Using the CMPSS
      1. 13.6.1 LATCHCLR and EPWMSYNCPER Signals
      2. 13.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 13.6.3 Calibrating the CMPSS
      4. 13.6.4 Enabling and Disabling the CMPSS Clock
    7. 13.7 Software
      1. 13.7.1 CMPSS Examples
        1. 13.7.1.1 CMPSS Asynchronous Trip
        2. 13.7.1.2 CMPSS Digital Filter Configuration
    8. 13.8 CMPSS Registers
      1. 13.8.1 CMPSS Base Addresses
      2. 13.8.2 CMPSS_REGS Registers
      3. 13.8.3 CMPSS Registers to Driverlib Functions
  16. 14Sigma Delta Filter Module (SDFM)
    1. 14.1  Introduction
      1. 14.1.1 SDFM Related Collateral
      2. 14.1.2 Features
      3. 14.1.3 Block Diagram
    2. 14.2  Configuring Device Pins
    3. 14.3  Input Control Unit
    4. 14.4  Sinc Filter
      1. 14.4.1 Data Rate and Latency of the Sinc Filter
    5. 14.5  Data (Primary) Filter Unit
      1. 14.5.1 32-bit or 16-bit Data Filter Output Representation
      2. 14.5.2 SDSYNC Event
    6. 14.6  Comparator (Secondary) Filter Unit
      1. 14.6.1 Higher Threshold (HLT) Comparator
      2. 14.6.2 Lower Threshold (LLT) Comparator
    7. 14.7  Theoretical SDFM Filter Output
    8. 14.8  Interrupt Unit
      1. 14.8.1 SDFM (SDINT) Interrupt Sources
    9. 14.9  Register Descriptions
    10. 14.10 Software
      1. 14.10.1 SDFM Examples
    11. 14.11 SDFM Registers
      1. 14.11.1 SDFM Base Addresses
      2. 14.11.2 SDFM_REGS Registers
      3. 14.11.3 SDFM Registers to Driverlib Functions
  17. 15Enhanced Pulse Width Modulator (ePWM)
    1. 15.1  Introduction
      1. 15.1.1 EPWM Related Collateral
      2. 15.1.2 Submodule Overview
    2. 15.2  Configuring Device Pins
    3. 15.3  ePWM Modules Overview
    4. 15.4  Time-Base (TB) Submodule
      1. 15.4.1 Purpose of the Time-Base Submodule
      2. 15.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 15.4.3 Calculating PWM Period and Frequency
        1. 15.4.3.1 Time-Base Period Shadow Register
        2. 15.4.3.2 Time-Base Clock Synchronization
        3. 15.4.3.3 Time-Base Counter Synchronization
      4. 15.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 15.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 15.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 15.4.7 Global Load
        1. 15.4.7.1 Global Load Pulse Pre-Scalar
        2. 15.4.7.2 One-Shot Load Mode
        3. 15.4.7.3 One-Shot Sync Mode
    5. 15.5  Counter-Compare (CC) Submodule
      1. 15.5.1 Purpose of the Counter-Compare Submodule
      2. 15.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 15.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 15.5.4 Count Mode Timing Waveforms
    6. 15.6  Action-Qualifier (AQ) Submodule
      1. 15.6.1 Purpose of the Action-Qualifier Submodule
      2. 15.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 15.6.3 Action-Qualifier Event Priority
      4. 15.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 15.6.5 Configuration Requirements for Common Waveforms
    7. 15.7  Dead-Band Generator (DB) Submodule
      1. 15.7.1 Purpose of the Dead-Band Submodule
      2. 15.7.2 Dead-band Submodule Additional Operating Modes
      3. 15.7.3 Operational Highlights for the Dead-Band Submodule
    8. 15.8  PWM Chopper (PC) Submodule
      1. 15.8.1 Purpose of the PWM Chopper Submodule
      2. 15.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 15.8.3 Waveforms
        1. 15.8.3.1 One-Shot Pulse
        2. 15.8.3.2 Duty Cycle Control
    9. 15.9  Trip-Zone (TZ) Submodule
      1. 15.9.1 Purpose of the Trip-Zone Submodule
      2. 15.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 15.9.2.1 Trip-Zone Configurations
      3. 15.9.3 Generating Trip Event Interrupts
    10. 15.10 Event-Trigger (ET) Submodule
      1. 15.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 15.11 Digital Compare (DC) Submodule
      1. 15.11.1 Purpose of the Digital Compare Submodule
      2. 15.11.2 Enhanced Trip Action Using CMPSS
      3. 15.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 15.11.4 Operation Highlights of the Digital Compare Submodule
        1. 15.11.4.1 Digital Compare Events
        2. 15.11.4.2 Event Filtering
        3. 15.11.4.3 Valley Switching
    12. 15.12 ePWM Crossbar (X-BAR)
    13. 15.13 Applications to Power Topologies
      1. 15.13.1  Overview of Multiple Modules
      2. 15.13.2  Key Configuration Capabilities
      3. 15.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 15.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 15.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 15.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 15.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 15.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 15.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 15.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 15.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 15.14 High-Resolution Pulse Width Modulator (HRPWM)
      1. 15.14.1 Operational Description of HRPWM
        1. 15.14.1.1 Controlling the HRPWM Capabilities
        2. 15.14.1.2 HRPWM Source Clock
        3. 15.14.1.3 Configuring the HRPWM
        4. 15.14.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 15.14.1.5 Principle of Operation
          1. 15.14.1.5.1 Edge Positioning
          2. 15.14.1.5.2 Scaling Considerations
          3. 15.14.1.5.3 Duty Cycle Range Limitation
          4. 15.14.1.5.4 High-Resolution Period
            1. 15.14.1.5.4.1 High-Resolution Period Configuration
        6. 15.14.1.6 Deadband High-Resolution Operation
        7. 15.14.1.7 Scale Factor Optimizing Software (SFO)
        8. 15.14.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 15.14.1.8.1 #Defines for HRPWM Header Files
          2. 15.14.1.8.2 Implementing a Simple Buck Converter
            1. 15.14.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 15.14.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 15.14.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 15.14.1.8.3.1 PWM DAC Function Initialization Code
            2. 15.14.1.8.3.2 PWM DAC Function Run-Time Code
      2. 15.14.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 15.14.2.1 Scale Factor Optimizer Function - int SFO()
        2. 15.14.2.2 Software Usage
          1. 15.14.2.2.1 A Sample of How to Add "Include" Files
          2.        762
          3. 15.14.2.2.2 Declaring an Element
          4.        764
          5. 15.14.2.2.3 Initializing With a Scale Factor Value
          6.        766
          7. 15.14.2.2.4 SFO Function Calls
    15. 15.15 ePWM Registers
      1. 15.15.1 ePWM Base Addresses
      2. 15.15.2 EPWM_REGS Registers
      3. 15.15.3 Register to Driverlib Function Mapping
        1. 15.15.3.1 EPWM Registers to Driverlib Functions
        2. 15.15.3.2 HRPWM Registers to Driverlib Functions
  18. 16Enhanced Capture (eCAP)
    1. 16.1 Introduction
      1. 16.1.1 Features
      2. 16.1.2 ECAP Related Collateral
    2. 16.2 Description
    3. 16.3 Configuring Device Pins for the eCAP
    4. 16.4 Capture and APWM Operating Mode
    5. 16.5 Capture Mode Description
      1. 16.5.1  Event Prescaler
      2. 16.5.2  Edge Polarity Select and Qualifier
      3. 16.5.3  Continuous/One-Shot Control
      4. 16.5.4  32-Bit Counter and Phase Control
      5. 16.5.5  CAP1-CAP4 Registers
      6. 16.5.6  eCAP Synchronization
        1. 16.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 16.5.7  Interrupt Control
      8. 16.5.8  DMA Interrupt
      9. 16.5.9  Shadow Load and Lockout Control
      10. 16.5.10 APWM Mode Operation
    6. 16.6 Application of the eCAP Module
      1. 16.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 16.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 16.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 16.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 16.7 Application of the APWM Mode
      1. 16.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 16.8 Software
      1. 16.8.1 ECAP Examples
        1. 16.8.1.1 eCAP APWM Example
        2. 16.8.1.2 eCAP Capture PWM Example
        3. 16.8.1.3 eCAP APWM Phase-shift Example
        4. 16.8.1.4 eCAP Software Sync Example
    9. 16.9 eCAP Registers
      1. 16.9.1 eCAP Base Addresses
      2. 16.9.2 ECAP_REGS Registers
      3. 16.9.3 ECAP Registers to Driverlib Functions
  19. 17Enhanced Quadrature Encoder Pulse (eQEP)
    1. 17.1  Introduction
      1. 17.1.1 EQEP Related Collateral
    2. 17.2  Configuring Device Pins
    3. 17.3  Description
      1. 17.3.1 EQEP Inputs
      2. 17.3.2 Functional Description
      3. 17.3.3 eQEP Memory Map
    4. 17.4  Quadrature Decoder Unit (QDU)
      1. 17.4.1 Position Counter Input Modes
        1. 17.4.1.1 Quadrature Count Mode
        2. 17.4.1.2 Direction-Count Mode
        3. 17.4.1.3 Up-Count Mode
        4. 17.4.1.4 Down-Count Mode
      2. 17.4.2 eQEP Input Polarity Selection
      3. 17.4.3 Position-Compare Sync Output
    5. 17.5  Position Counter and Control Unit (PCCU)
      1. 17.5.1 Position Counter Operating Modes
        1. 17.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 17.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 17.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 17.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 17.5.2 Position Counter Latch
        1. 17.5.2.1 Index Event Latch
        2. 17.5.2.2 Strobe Event Latch
      3. 17.5.3 Position Counter Initialization
      4. 17.5.4 eQEP Position-compare Unit
    6. 17.6  eQEP Edge Capture Unit
    7. 17.7  eQEP Watchdog
    8. 17.8  eQEP Unit Timer Base
    9. 17.9  eQEP Interrupt Structure
    10. 17.10 eQEP Registers
      1. 17.10.1 eQEP Base Addresses
      2. 17.10.2 EQEP_REGS Registers
      3. 17.10.3 EQEP Registers to Driverlib Functions
  20. 18Serial Peripheral Interface (SPI)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 SPI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2 System-Level Integration
      1. 18.2.1 SPI Module Signals
      2. 18.2.2 Configuring Device Pins
        1. 18.2.2.1 GPIOs Required for High-Speed Mode
      3. 18.2.3 SPI Interrupts
      4. 18.2.4 DMA Support
    3. 18.3 SPI Operation
      1. 18.3.1  Introduction to Operation
      2. 18.3.2  Master Mode
      3. 18.3.3  Slave Mode
      4. 18.3.4  Data Format
        1. 18.3.4.1 Transmission of Bit from SPIRXBUF
      5. 18.3.5  Baud Rate Selection
        1. 18.3.5.1 Baud Rate Determination
        2. 18.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 18.3.6  SPI Clocking Schemes
      7. 18.3.7  SPI FIFO Description
      8. 18.3.8  SPI DMA Transfers
        1. 18.3.8.1 Transmitting Data Using SPI with DMA
        2. 18.3.8.2 Receiving Data Using SPI with DMA
      9. 18.3.9  SPI High-Speed Mode
      10. 18.3.10 SPI 3-Wire Mode Description
    4. 18.4 Programming Procedure
      1. 18.4.1 Initialization Upon Reset
      2. 18.4.2 Configuring the SPI
      3. 18.4.3 Configuring the SPI for High-Speed Mode
      4. 18.4.4 Data Transfer Example
      5. 18.4.5 SPI 3-Wire Mode Code Examples
        1. 18.4.5.1 3-Wire Master Mode Transmit
        2.       879
          1. 18.4.5.2.1 3-Wire Master Mode Receive
        3.       881
          1. 18.4.5.2.1 3-Wire Slave Mode Transmit
        4.       883
          1. 18.4.5.2.1 3-Wire Slave Mode Receive
      6. 18.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 18.5 Software
      1. 18.5.1 SPI Examples
        1. 18.5.1.1 SPI Digital Loopback
        2. 18.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 18.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 18.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 18.5.1.5 SPI Digital Loopback with DMA
        6. 18.5.1.6 SPI EEPROM
        7. 18.5.1.7 SPI DMA EEPROM
    6. 18.6 SPI Registers
      1. 18.6.1 SPI Base Addresses
      2. 18.6.2 SPI_REGS Registers
      3. 18.6.3 SPI Registers to Driverlib Functions
  21. 19Serial Communications Interface (SCI)
    1. 19.1  Introduction
      1. 19.1.1 Features
      2. 19.1.2 SCI Related Collateral
      3. 19.1.3 Block Diagram
    2. 19.2  Architecture
    3. 19.3  SCI Module Signal Summary
    4. 19.4  Configuring Device Pins
    5. 19.5  Multiprocessor and Asynchronous Communication Modes
    6. 19.6  SCI Programmable Data Format
    7. 19.7  SCI Multiprocessor Communication
      1. 19.7.1 Recognizing the Address Byte
      2. 19.7.2 Controlling the SCI TX and RX Features
      3. 19.7.3 Receipt Sequence
    8. 19.8  Idle-Line Multiprocessor Mode
      1. 19.8.1 Idle-Line Mode Steps
      2. 19.8.2 Block Start Signal
      3. 19.8.3 Wake-Up Temporary (WUT) Flag
        1. 19.8.3.1 Sending a Block Start Signal
      4. 19.8.4 Receiver Operation
    9. 19.9  Address-Bit Multiprocessor Mode
      1. 19.9.1 Sending an Address
    10. 19.10 SCI Communication Format
      1. 19.10.1 Receiver Signals in Communication Modes
      2. 19.10.2 Transmitter Signals in Communication Modes
    11. 19.11 SCI Port Interrupts
      1. 19.11.1 Break Detect
    12. 19.12 SCI Baud Rate Calculations
    13. 19.13 SCI Enhanced Features
      1. 19.13.1 SCI FIFO Description
      2. 19.13.2 SCI Auto-Baud
      3. 19.13.3 Autobaud-Detect Sequence
    14. 19.14 Software
      1. 19.14.1 SCI Examples
    15. 19.15 SCI Registers
      1. 19.15.1 SCI Base Addresses
      2. 19.15.2 SCI_REGS Registers
      3. 19.15.3 SCI Registers to Driverlib Functions
  22. 20Inter-Integrated Circuit Module (I2C)
    1. 20.1 Introduction
      1. 20.1.1 I2C Related Collateral
      2. 20.1.2 Features
      3. 20.1.3 Features Not Supported
      4. 20.1.4 Functional Overview
      5. 20.1.5 Clock Generation
      6. 20.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 20.1.6.1 Formula for the Master Clock Period
    2. 20.2 Configuring Device Pins
    3. 20.3 I2C Module Operational Details
      1. 20.3.1  Input and Output Voltage Levels
      2. 20.3.2  Selecting Pullup Resistors
      3. 20.3.3  Data Validity
      4. 20.3.4  Operating Modes
      5. 20.3.5  I2C Module START and STOP Conditions
      6. 20.3.6  Non-repeat Mode versus Repeat Mode
      7. 20.3.7  Serial Data Formats
        1. 20.3.7.1 7-Bit Addressing Format
        2. 20.3.7.2 10-Bit Addressing Format
        3. 20.3.7.3 Free Data Format
        4. 20.3.7.4 Using a Repeated START Condition
      8. 20.3.8  Clock Synchronization
      9. 20.3.9  Arbitration
      10. 20.3.10 Digital Loopback Mode
      11. 20.3.11 NACK Bit Generation
    4. 20.4 Interrupt Requests Generated by the I2C Module
      1. 20.4.1 Basic I2C Interrupt Requests
      2. 20.4.2 I2C FIFO Interrupts
    5. 20.5 Resetting or Disabling the I2C Module
    6. 20.6 Software
      1. 20.6.1 I2C Examples
        1. 20.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 20.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 20.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 20.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 20.6.1.5 I2C EEPROM
        6. 20.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 20.6.1.7 I2C EEPROM
        8. 20.6.1.8 I2C controller target communication using FIFO interrupts
        9. 20.6.1.9 I2C EEPROM
    7. 20.7 I2C Registers
      1. 20.7.1 I2C Base Addresses
      2. 20.7.2 I2C_REGS Registers
      3. 20.7.3 I2C Registers to Driverlib Functions
  23. 21Multichannel Buffered Serial Port (McBSP)
    1. 21.1  Introduction
      1. 21.1.1 MCBSP Related Collateral
      2. 21.1.2 Features of the McBSPs
      3. 21.1.3 McBSP Pins/Signals
        1. 21.1.3.1 McBSP Generic Block Diagram
    2. 21.2  Configuring Device Pins
    3. 21.3  McBSP Operation
      1. 21.3.1 Data Transfer Process of McBSPs
        1. 21.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 21.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 21.3.2 Companding (Compressing and Expanding) Data
        1. 21.3.2.1 Companding Formats
        2. 21.3.2.2 Capability to Compand Internal Data
        3. 21.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 21.3.3 Clocking and Framing Data
        1. 21.3.3.1 Clocking
        2. 21.3.3.2 Serial Words
        3. 21.3.3.3 Frames and Frame Synchronization
        4. 21.3.3.4 Generating Transmit and Receive Interrupts
          1. 21.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 21.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 21.3.3.6 Frame Frequency
        7. 21.3.3.7 Maximum Frame Frequency
      4. 21.3.4 Frame Phases
        1. 21.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 21.3.4.2 Single-Phase Frame Example
        3. 21.3.4.3 Dual-Phase Frame Example
        4. 21.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 21.3.5 McBSP Reception
      6. 21.3.6 McBSP Transmission
      7. 21.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 21.4  McBSP Sample Rate Generator
      1. 21.4.1 Block Diagram
        1. 21.4.1.1 Clock Generation in the Sample Rate Generator
        2. 21.4.1.2 Choosing an Input Clock
        3. 21.4.1.3 Choosing a Polarity for the Input Clock
        4. 21.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 21.4.1.4.1 CLKG Frequency
        5. 21.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 21.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 21.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 21.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 21.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 21.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 21.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 21.4.3.2 Synchronization Examples
      4. 21.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 21.5  McBSP Exception/Error Conditions
      1. 21.5.1 Types of Errors
      2. 21.5.2 Overrun in the Receiver
        1. 21.5.2.1 Example of Overrun Condition
        2. 21.5.2.2 Example of Preventing Overrun Condition
      3. 21.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 21.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 21.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 21.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 21.5.4 Overwrite in the Transmitter
        1. 21.5.4.1 Example of Overwrite Condition
        2. 21.5.4.2 Preventing Overwrites
      5. 21.5.5 Underflow in the Transmitter
        1. 21.5.5.1 Example of the Underflow Condition
        2. 21.5.5.2 Example of Preventing Underflow Condition
      6. 21.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 21.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 21.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 21.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 21.6  Multichannel Selection Modes
      1. 21.6.1 Channels, Blocks, and Partitions
      2. 21.6.2 Multichannel Selection
      3. 21.6.3 Configuring a Frame for Multichannel Selection
      4. 21.6.4 Using Two Partitions
        1. 21.6.4.1 Assigning Blocks to Partitions A and B
        2. 21.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 21.6.5 Using Eight Partitions
      6. 21.6.6 Receive Multichannel Selection Mode
      7. 21.6.7 Transmit Multichannel Selection Modes
        1. 21.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 21.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 21.6.8 Using Interrupts Between Block Transfers
    7. 21.7  SPI Operation Using the Clock Stop Mode
      1. 21.7.1 SPI Protocol
      2. 21.7.2 Clock Stop Mode
      3. 21.7.3 Enable and Configure the Clock Stop Mode
      4. 21.7.4 Clock Stop Mode Timing Diagrams
      5. 21.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 21.7.6 McBSP as the SPI Master
      7. 21.7.7 McBSP as an SPI Slave
    8. 21.8  Receiver Configuration
      1. 21.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 21.8.2  Resetting and Enabling the Receiver
        1. 21.8.2.1 Reset Considerations
      3. 21.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 21.8.4  Digital Loopback Mode
      5. 21.8.5  Clock Stop Mode
      6. 21.8.6  Receive Multichannel Selection Mode
      7. 21.8.7  Receive Frame Phases
      8. 21.8.8  Receive Word Lengths
        1. 21.8.8.1 Word Length Bits
      9. 21.8.9  Receive Frame Length
        1. 21.8.9.1 Selected Frame Length
      10. 21.8.10 Receive Frame-Synchronization Ignore Function
        1. 21.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 21.8.10.2 Examples of Effects of RFIG
      11. 21.8.11 Receive Companding Mode
        1. 21.8.11.1 Companding
        2. 21.8.11.2 Format of Expanded Data
        3. 21.8.11.3 Companding Internal Data
        4. 21.8.11.4 Option to Receive LSB First
      12. 21.8.12 Receive Data Delay
        1. 21.8.12.1 Data Delay
        2. 21.8.12.2 0-Bit Data Delay
        3. 21.8.12.3 2-Bit Data Delay
      13. 21.8.13 Receive Sign-Extension and Justification Mode
        1. 21.8.13.1 Sign-Extension and the Justification
      14. 21.8.14 Receive Interrupt Mode
      15. 21.8.15 Receive Frame-Synchronization Mode
        1. 21.8.15.1 Receive Frame-Synchronization Modes
      16. 21.8.16 Receive Frame-Synchronization Polarity
        1. 21.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 21.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 21.8.17 Receive Clock Mode
        1. 21.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 21.8.18 Receive Clock Polarity
        1. 21.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 21.8.19 SRG Clock Divide-Down Value
        1. 21.8.19.1 Sample Rate Generator Clock Divider
      20. 21.8.20 SRG Clock Synchronization Mode
      21. 21.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 21.8.22 SRG Input Clock Polarity
        1. 21.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 21.9  Transmitter Configuration
      1. 21.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 21.9.2  Resetting and Enabling the Transmitter
        1. 21.9.2.1 Reset Considerations
      3. 21.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 21.9.4  Digital Loopback Mode
      5. 21.9.5  Clock Stop Mode
      6. 21.9.6  Transmit Multichannel Selection Mode
      7. 21.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 21.9.8  Transmit Frame Phases
      9. 21.9.9  Transmit Word Lengths
        1. 21.9.9.1 Word Length Bits
      10. 21.9.10 Transmit Frame Length
        1. 21.9.10.1 Selected Frame Length
      11. 21.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 21.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 21.9.11.2 Examples Showing the Effects of XFIG
      12. 21.9.12 Transmit Companding Mode
        1. 21.9.12.1 Companding
        2. 21.9.12.2 Format for Data To Be Compressed
        3. 21.9.12.3 Capability to Compand Internal Data
        4. 21.9.12.4 Option to Transmit LSB First
      13. 21.9.13 Transmit Data Delay
        1. 21.9.13.1 Data Delay
        2. 21.9.13.2 0-Bit Data Delay
        3. 21.9.13.3 2-Bit Data Delay
      14. 21.9.14 Transmit DXENA Mode
      15. 21.9.15 Transmit Interrupt Mode
      16. 21.9.16 Transmit Frame-Synchronization Mode
        1. 21.9.16.1 Other Considerations
      17. 21.9.17 Transmit Frame-Synchronization Polarity
        1. 21.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 21.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 21.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 21.9.19 Transmit Clock Mode
        1. 21.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 21.9.19.2 Other Considerations
      20. 21.9.20 Transmit Clock Polarity
        1. 21.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 21.10 Emulation and Reset Considerations
      1. 21.10.1 McBSP Emulation Mode
      2. 21.10.2 Resetting and Initializing McBSPs
        1. 21.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 21.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 21.10.2.3 McBSP Initialization Procedure
        4. 21.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 21.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 21.11 Data Packing Examples
      1. 21.11.1 Data Packing Using Frame Length and Word Length
      2. 21.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 21.12 Interrupt Generation
      1. 21.12.1 McBSP Receive Interrupt Generation
      2. 21.12.2 McBSP Transmit Interrupt Generation
      3. 21.12.3 Error Flags
    13. 21.13 McBSP Modes
    14. 21.14 Special Case: External Device is the Transmit Frame Master
    15. 21.15 Software
      1. 21.15.1 MCBSP Examples
    16. 21.16 McBSP Registers
      1. 21.16.1 McBSP Base Addresses
      2. 21.16.2 McBSP_REGS Registers
      3. 21.16.3 MCBSP Registers to Driverlib Functions
  24. 22Controller Area Network (CAN)
    1. 22.1  Introduction
      1. 22.1.1 DCAN Related Collateral
      2. 22.1.2 Features
      3. 22.1.3 Block Diagram
        1. 22.1.3.1 CAN Core
        2. 22.1.3.2 Message Handler
        3. 22.1.3.3 Message RAM
        4. 22.1.3.4 Registers and Message Object Access (IFx)
    2. 22.2  Functional Description
      1. 22.2.1 Configuring Device Pins
      2. 22.2.2 Address/Data Bus Bridge
    3. 22.3  Operating Modes
      1. 22.3.1 Initialization
      2. 22.3.2 CAN Message Transfer (Normal Operation)
        1. 22.3.2.1 Disabled Automatic Retransmission
        2. 22.3.2.2 Auto-Bus-On
      3. 22.3.3 Test Modes
        1. 22.3.3.1 Silent Mode
        2. 22.3.3.2 Loopback Mode
        3. 22.3.3.3 External Loopback Mode
        4. 22.3.3.4 Loopback Combined with Silent Mode
    4. 22.4  Multiple Clock Source
    5. 22.5  Interrupt Functionality
      1. 22.5.1 Message Object Interrupts
      2. 22.5.2 Status Change Interrupts
      3. 22.5.3 Error Interrupts
      4. 22.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 22.5.5 Interrupt Topologies
    6. 22.6  Parity Check Mechanism
      1. 22.6.1 Behavior on Parity Error
    7. 22.7  Debug Mode
    8. 22.8  Module Initialization
    9. 22.9  Configuration of Message Objects
      1. 22.9.1 Configuration of a Transmit Object for Data Frames
      2. 22.9.2 Configuration of a Transmit Object for Remote Frames
      3. 22.9.3 Configuration of a Single Receive Object for Data Frames
      4. 22.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 22.9.5 Configuration of a FIFO Buffer
    10. 22.10 Message Handling
      1. 22.10.1  Message Handler Overview
      2. 22.10.2  Receive/Transmit Priority
      3. 22.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 22.10.4  Updating a Transmit Object
      5. 22.10.5  Changing a Transmit Object
      6. 22.10.6  Acceptance Filtering of Received Messages
      7. 22.10.7  Reception of Data Frames
      8. 22.10.8  Reception of Remote Frames
      9. 22.10.9  Reading Received Messages
      10. 22.10.10 Requesting New Data for a Receive Object
      11. 22.10.11 Storing Received Messages in FIFO Buffers
      12. 22.10.12 Reading from a FIFO Buffer
    11. 22.11 CAN Bit Timing
      1. 22.11.1 Bit Time and Bit Rate
        1. 22.11.1.1 Synchronization Segment
        2. 22.11.1.2 Propagation Time Segment
        3. 22.11.1.3 Phase Buffer Segments and Synchronization
        4. 22.11.1.4 Oscillator Tolerance Range
      2. 22.11.2 Configuration of the CAN Bit Timing
        1. 22.11.2.1 Calculation of the Bit Timing Parameters
        2. 22.11.2.2 Example for Bit Timing at High Baudrate
        3. 22.11.2.3 Example for Bit Timing at Low Baudrate
    12. 22.12 Message Interface Register Sets
      1. 22.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 22.12.2 Message Interface Register Set 3 (IF3)
    13. 22.13 Message RAM
      1. 22.13.1 Structure of Message Objects
      2. 22.13.2 Addressing Message Objects in RAM
      3. 22.13.3 Message RAM Representation in Debug Mode
    14. 22.14 Software
      1. 22.14.1 CAN Examples
    15. 22.15 CAN Registers
      1. 22.15.1 CAN Base Addresses
      2. 22.15.2 CAN_REGS Registers
      3. 22.15.3 CAN Registers to Driverlib Functions
  25. 23Universal Serial Bus (USB) Controller
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 USB Related Collateral
      3. 23.1.3 Block Diagram
        1. 23.1.3.1 Signal Description
        2. 23.1.3.2 VBus Recommendations
    2. 23.2 Functional Description
      1. 23.2.1 Operation as a Device
        1. 23.2.1.1 Control and Configurable Endpoints
          1. 23.2.1.1.1 IN Transactions as a Device
          2. 23.2.1.1.2 Out Transactions as a Device
          3. 23.2.1.1.3 Scheduling
          4. 23.2.1.1.4 Additional Actions
          5. 23.2.1.1.5 Device Mode Suspend
          6. 23.2.1.1.6 Start of Frame
          7. 23.2.1.1.7 USB Reset
          8. 23.2.1.1.8 Connect/Disconnect
      2. 23.2.2 Operation as a Host
        1. 23.2.2.1 Endpoint Registers
        2. 23.2.2.2 IN Transactions as a Host
        3. 23.2.2.3 OUT Transactions as a Host
        4. 23.2.2.4 Transaction Scheduling
        5. 23.2.2.5 USB Hubs
        6. 23.2.2.6 Babble
        7. 23.2.2.7 Host SUSPEND
        8. 23.2.2.8 USB RESET
        9. 23.2.2.9 Connect/Disconnect
      3. 23.2.3 DMA Operation
      4. 23.2.4 Address/Data Bus Bridge
    3. 23.3 Initialization and Configuration
      1. 23.3.1 Pin Configuration
      2. 23.3.2 Endpoint Configuration
    4. 23.4 USB Global Interrupts
    5. 23.5 Software
      1. 23.5.1 USB Examples
    6. 23.6 USB Registers
      1. 23.6.1 USB Base Address
      2. 23.6.2 USB Register Map
      3. 23.6.3 Register Descriptions
        1. 23.6.3.1  USB Device Functional Address Register (USBFADDR), offset 0x000
        2. 23.6.3.2  USB Power Management Register (USBPOWER), offset 0x001
        3. 23.6.3.3  USB Transmit Interrupt Status Register
        4. 23.6.3.4  USB Receive Interrupt Status Register
        5. 23.6.3.5  USB Transmit Interrupt Enable Register
        6. 23.6.3.6  USB Receive Interrupt Enable Register
        7. 23.6.3.7  USB General Interrupt Status Register (USBIS), offset 0x00A
        8. 23.6.3.8  USB Interrupt Enable Register (USBIE), offset 0x00B
        9. 23.6.3.9  USB Frame Value Register (USBFRAME), offset 0x00C
        10. 23.6.3.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
        11. 23.6.3.11 USB Test Mode Register (USBTEST), offset 0x00F
        12. 23.6.3.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
        13. 23.6.3.13 USB Device Control Register (USBDEVCTL), offset 0x060
        14. 23.6.3.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
        15. 23.6.3.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
        16. 23.6.3.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
        17. 23.6.3.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
        18. 23.6.3.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
        19. 23.6.3.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
        20. 23.6.3.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
        21. 23.6.3.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[n])
        22. 23.6.3.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[n])
        23. 23.6.3.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[n])
        24. 23.6.3.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[n)
        25. 23.6.3.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[n])
        26. 23.6.3.26 USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[1]-USBRXHUBPORT[n])
        27. 23.6.3.27 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
        28. 23.6.3.28 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
        29. 23.6.3.29 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
        30. 23.6.3.30 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
        31. 23.6.3.31 USB NAK Limit Register (USBNAKLMT), offset 0x10B
        32. 23.6.3.32 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[n])
        33. 23.6.3.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[n])
        34. 23.6.3.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[n])
        35. 23.6.3.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[n])
        36. 23.6.3.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[n])
        37. 23.6.3.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[n])
        38. 23.6.3.38 USB Receive Byte Count Endpoint n Register (USBRXCOUNT[1]-USBRXCOUNT[n])
        39. 23.6.3.39 USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[1]-USBTXTYPE[n])
        40. 23.6.3.40 USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[1]-USBTXINTERVAL[n])
        41. 23.6.3.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[n])
        42. 23.6.3.42 USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[1]-USBRXINTERVAL[n])
        43. 23.6.3.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[n])
        44. 23.6.3.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
        45. 23.6.3.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
        46. 23.6.3.46 USB External Power Control Register (USBEPC), offset 0x400
        47. 23.6.3.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
        48. 23.6.3.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
        49. 23.6.3.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
        50. 23.6.3.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
        51. 23.6.3.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
        52. 23.6.3.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
        53. 23.6.3.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
        54. 23.6.3.54 USB DMA Select Register (USBDMASEL), offset 0x450
      4. 23.6.4 USB Registers to Driverlib Functions
  26. 24Universal Parallel Port (uPP)
    1. 24.1 Introduction
      1. 24.1.1 Features Supported
    2. 24.2 Configuring Device Pins
    3. 24.3 Functional Description
      1. 24.3.1 Functional Block Diagram
      2. 24.3.2 Data Flow
      3. 24.3.3 Clock Generation and Control
    4. 24.4 IO Interface and System Requirements
      1. 24.4.1  Pin Multiplexing
      2. 24.4.2  Internal DMA Controller Description
        1. 24.4.2.1 DMA Programming Concepts
        2. 24.4.2.2 Data Interleave Mode
      3. 24.4.3  Protocol Description
        1. 24.4.3.1 DATA[7:0] Signals
        2. 24.4.3.2 START Signal
        3. 24.4.3.3 ENABLE
        4. 24.4.3.4 WAIT Signal
        5. 24.4.3.5 CLOCK Signal
        6. 24.4.3.6 Signal Timing Diagrams
      4. 24.4.4  Data Format
      5. 24.4.5  Reset Considerations
        1. 24.4.5.1 Software Reset
        2. 24.4.5.2 Hardware Reset
      6. 24.4.6  Interrupt Support
        1. 24.4.6.1 End of Line (EOL) Event
        2. 24.4.6.2 End of Window (EOW) Event
        3. 24.4.6.3 Underrun or Overflow (UOR) Event
        4. 24.4.6.4 DMA Programming Error (DPE) Event
      7. 24.4.7  Emulation Considerations
      8. 24.4.8  Transmit and Receive FIFOs
      9. 24.4.9  Transmit and Receive Data (MSG) RAM
      10. 24.4.10 Initialization and Operation
        1. 24.4.10.1 System Tuning Tips
    5. 24.5 UPP Registers
      1. 24.5.1 UPP Base Addresses
      2. 24.5.2 UPP_REGS Registers
      3. 24.5.3 UPP Registers to Driverlib Functions
  27. 25External Memory Interface (EMIF)
    1. 25.1 Introduction
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 EMIF Related Collateral
      3. 25.1.3 Features
        1. 25.1.3.1 Asynchronous Memory Support
        2. 25.1.3.2 Synchronous DRAM Memory Support
      4. 25.1.4 Functional Block Diagram
      5. 25.1.5 Configuring Device Pins
    2. 25.2 EMIF Module Architecture
      1. 25.2.1  EMIF Clock Control
      2. 25.2.2  EMIF Requests
      3. 25.2.3  EMIF Signal Descriptions
      4. 25.2.4  EMIF Signal Multiplexing Control
      5. 25.2.5  SDRAM Controller and Interface
        1. 25.2.5.1  SDRAM Commands
        2. 25.2.5.2  Interfacing to SDRAM
        3. 25.2.5.3  SDRAM Configuration Registers
        4. 25.2.5.4  SDRAM Auto-Initialization Sequence
        5. 25.2.5.5  SDRAM Configuration Procedure
        6. 25.2.5.6  EMIF Refresh Controller
          1. 25.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 25.2.5.7  Self-Refresh Mode
        8. 25.2.5.8  Power-Down Mode
        9. 25.2.5.9  SDRAM Read Operation
        10. 25.2.5.10 SDRAM Write Operations
        11. 25.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 25.2.6  Asynchronous Controller and Interface
        1. 25.2.6.1 Interfacing to Asynchronous Memory
        2. 25.2.6.2 Accessing Larger Asynchronous Memories
        3. 25.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 25.2.6.4 Read and Write Operations in Normal Mode
          1. 25.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 25.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 25.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 25.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 25.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 25.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 25.2.7  Data Bus Parking
      8. 25.2.8  Reset and Initialization Considerations
      9. 25.2.9  Interrupt Support
        1. 25.2.9.1 Interrupt Events
      10. 25.2.10 DMA Event Support
      11. 25.2.11 EMIF Signal Multiplexing
      12. 25.2.12 Memory Map
      13. 25.2.13 Priority and Arbitration
      14. 25.2.14 System Considerations
        1. 25.2.14.1 Asynchronous Request Times
      15. 25.2.15 Power Management
        1. 25.2.15.1 Power Management Using Self-Refresh Mode
        2. 25.2.15.2 Power Management Using Power Down Mode
      16. 25.2.16 Emulation Considerations
    3. 25.3 Example Configuration
      1. 25.3.1 Hardware Interface
      2. 25.3.2 Software Configuration
        1. 25.3.2.1 Configuring the SDRAM Interface
          1. 25.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 25.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 25.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 25.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 25.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 25.3.2.2 Configuring the Flash Interface
          1. 25.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 25.4 EMIF Registers
      1. 25.4.1 EMIF Base Addresses
      2. 25.4.2 EMIF_REGS Registers
      3. 25.4.3 EMIF1_CONFIG_REGS Registers
      4. 25.4.4 EMIF2_CONFIG_REGS Registers
      5. 25.4.5 EMIF Registers to Driverlib Functions
  28. 26Configurable Logic Block (CLB)
    1. 26.1 Introduction
      1. 26.1.1 CLB Related Collateral
    2. 26.2 Description
      1. 26.2.1 CLB Clock
    3. 26.3 CLB Input/Output Connection
      1. 26.3.1 Overview
      2. 26.3.2 CLB Input Selection
      3. 26.3.3 CLB Output Selection
      4. 26.3.4 CLB Output Signal Multiplexer
    4. 26.4 CLB Tile
      1. 26.4.1 Static Switch Block
      2. 26.4.2 Counter Block
        1. 26.4.2.1 Counter Description
        2. 26.4.2.2 Counter Operation
      3. 26.4.3 FSM Block
      4. 26.4.4 LUT4 Block
      5. 26.4.5 Output LUT Block
      6. 26.4.6 High Level Controller (HLC)
        1. 26.4.6.1 High Level Controller Events
        2. 26.4.6.2 High Level Controller Instructions
        3. 26.4.6.3 <Src> and <Dest>
        4. 26.4.6.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 26.5 CPU Interface
      1. 26.5.1 Register Description
      2. 26.5.2 Non-Memory Mapped Registers
    6. 26.6 DMA Access
    7. 26.7 Software
      1. 26.7.1 CLB Examples
        1. 26.7.1.1  CLB Empty Project
        2. 26.7.1.2  CLB Combinational Logic
        3. 26.7.1.3  CLB GPIO Input Filter
        4. 26.7.1.4  CLB Auxilary PWM
        5. 26.7.1.5  CLB PWM Protection
        6. 26.7.1.6  CLB Event Window
        7. 26.7.1.7  CLB Signal Generator
        8. 26.7.1.8  CLB State Machine
        9. 26.7.1.9  CLB External Signal AND Gate
        10. 26.7.1.10 CLB Timer
        11. 26.7.1.11 CLB Timer Two States
        12. 26.7.1.12 CLB Interrupt Tag
        13. 26.7.1.13 CLB Output Intersect
        14. 26.7.1.14 CLB PUSH PULL
        15. 26.7.1.15 CLB Multi Tile
        16. 26.7.1.16 CLB Tile to Tile Delay
        17. 26.7.1.17 CLB based One-shot PWM
        18. 26.7.1.18 CLB Trip Zone Timestamp
    8. 26.8 CLB Registers
      1. 26.8.1 CLB Base Addresses
      2. 26.8.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 26.8.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 26.8.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 26.8.5 CLB Registers to Driverlib Functions
  29. 27Revision History

22.15.2 CAN_REGS Registers

Table 22-8 lists the memory-mapped registers for the CAN_REGS registers. All register offset addresses not listed in Table 22-8 should be considered as reserved locations and the register contents should not be modified.

Table 22-8 CAN_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hCAN_CTLCAN Control RegisterGo
4hCAN_ESError and Status RegisterGo
8hCAN_ERRCError Counter RegisterGo
ChCAN_BTRBit Timing RegisterGo
10hCAN_INTInterrupt RegisterGo
14hCAN_TESTTest RegisterGo
1ChCAN_PERRCAN Parity Error Code RegisterGo
40hCAN_RAM_INITCAN RAM Initialization RegisterGo
50hCAN_GLB_INT_ENCAN Global Interrupt Enable RegisterGo
54hCAN_GLB_INT_FLGCAN Global Interrupt Flag RegisterGo
58hCAN_GLB_INT_CLRCAN Global Interrupt Clear RegisterGo
80hCAN_ABOTRAuto-Bus-On Time RegisterGo
84hCAN_TXRQ_XCAN Transmission Request RegisterGo
88hCAN_TXRQ_21CAN Transmission Request 2_1 RegisterGo
98hCAN_NDAT_XCAN New Data RegisterGo
9ChCAN_NDAT_21CAN New Data 2_1 RegisterGo
AChCAN_IPEN_XCAN Interrupt Pending RegisterGo
B0hCAN_IPEN_21CAN Interrupt Pending 2_1 RegisterGo
C0hCAN_MVAL_XCAN Message Valid RegisterGo
C4hCAN_MVAL_21CAN Message Valid 2_1 RegisterGo
D8hCAN_IP_MUX21CAN Interrupt Multiplexer 2_1 RegisterGo
100hCAN_IF1CMDIF1 Command RegisterGo
104hCAN_IF1MSKIF1 Mask RegisterGo
108hCAN_IF1ARBIF1 Arbitration RegisterGo
10ChCAN_IF1MCTLIF1 Message Control RegisterGo
110hCAN_IF1DATAIF1 Data A RegisterGo
114hCAN_IF1DATBIF1 Data B RegisterGo
120hCAN_IF2CMDIF2 Command RegisterGo
124hCAN_IF2MSKIF2 Mask RegisterGo
128hCAN_IF2ARBIF2 Arbitration RegisterGo
12ChCAN_IF2MCTLIF2 Message Control RegisterGo
130hCAN_IF2DATAIF2 Data A RegisterGo
134hCAN_IF2DATBIF2 Data B RegisterGo
140hCAN_IF3OBSIF3 Observation RegisterGo
144hCAN_IF3MSKIF3 Mask RegisterGo
148hCAN_IF3ARBIF3 Arbitration RegisterGo
14ChCAN_IF3MCTLIF3 Message Control RegisterGo
150hCAN_IF3DATAIF3 Data A RegisterGo
154hCAN_IF3DATBIF3 Data B RegisterGo
160hCAN_IF3UPDIF3 Update Enable RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 22-9 shows the codes that are used for access types in this section.

Table 22-9 CAN_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

22.15.2.1 CAN_CTL Register (Offset = 0h) [Reset = 00001401h]

CAN_CTL is shown in Figure 22-22 and described in Table 22-10.

Return to the Summary Table.

This register is used for configuring the CAN module in terms of interrupts, parity, debug-mode behavior etc.

Figure 22-22 CAN_CTL Register
3130292827262524
RESERVEDRESERVEDRESERVED
R-0hR/W-0hR/W-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDIE1INITDBG
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
15141312111098
SWRRESERVEDPMDABOIDS
R-0/W1C-0hR-0hR/W-5hR/W-0hR/W-0h
76543210
TestCCEDARRESERVEDEIESIEIE0Init
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 22-10 CAN_CTL Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25RESERVEDR/W0hReserved
24RESERVEDR/W0hReserved
23-21RESERVEDR0hReserved
20RESERVEDR/W0hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17IE1R/W0hInterrupt line 1 Enable

0 CANINT1 is disabled.

1 CANINT1 is enabled. Interrupts will assert CANINT1 line to 1
line remains active until pending interrupts are processed.

Reset type: SYSRSn

16INITDBGR0hDebug Mode Status Bit: This bit indicates the internal init state for a debug access

0 Not in debug mode, or debug mode requested but not entered.

1 Debug mode requested and internally entered
the CAN module is ready for debug accesses.

Reset type: SYSRSn

15SWRR-0/W1C0hSoftware Reset Enable Bit: This bit activates the software reset.

0 Normal Operation.

1 Module is forced to reset state. This bit will get cleared automatically one clock cycle after execution of software reset.

Note: To execute software reset, the following procedure is necessary:
1. Set INIT bit to shut down CAN communication.
2. Set SWR bit.

Note: This bit is write-protected by Init bit. If module is reset using the SWR bit, no user configuration is lost. Only status bits get reset along with logic which needs to be reset for the next CAN transaction. If module is reset using SOFTPRES register, entire module will get reset, including configuration registers.

Reset type: SYSRSn

14RESERVEDR0hReserved
13-10PMDR/W5hParity on/off

0101 Parity function disabled

Any other value - Parity function enabled

Reset type: SYSRSn

9ABOR/W0hAuto-Bus-On Enable

0 The Auto-Bus-On feature is disabled

1 The Auto-Bus-On feature is enabled

Reset type: SYSRSn

8IDSR/W0hInterruption Debug Support Enable

0 When Debug mode is requested, the CAN module will wait for a started transmission or reception to be completed before entering Debug mode

1 When Debug mode is requested, the CAN module will interrupt any transmission or reception, and enter Debug mode immediately.

Reset type: SYSRSn

7TestR/W0hTest Mode Enable

0 Disable Test Mode (Normal operation)

1 Enable Test Mode

Reset type: SYSRSn

6CCER/W0hConfiguration Change Enable

0 The CPU has no write access to the configuration registers.

1 The CPU has write access to the configuration registers (when Init bit is set).

Reset type: SYSRSn

5DARR/W0hDisable Automatic Retransmission

0 Automatic Retransmission of 'not successful' messages enabled.

1 Automatic Retransmission disabled.

Reset type: SYSRSn

4RESERVEDR0hReserved
3EIER/W0hError Interrupt Enable

0 Disabled - PER, BOff and EWarn bits cannot generate an interrupt.

1 Enabled - PER, BOff and EWarn bits can generate an interrupt at CANINT0 line and affect the Interrupt Register.

Reset type: SYSRSn

2SIER/W0hStatus Change Interrupt Enable

0 Disabled - RxOk, TxOk and LEC bits cannot generate an interrupt.

1 Enabled - RxOk, TxOk and LEC can generate an interrupt on the CANINT0 line

Reset type: SYSRSn

1IE0R/W0hInterrupt line 0 Enable

0 CANINT0 is disabled.

1 CANINT0 is enabled. Interrupts will assert CANINT0 line to 1
line remains active until pending interrupts are processed.

Reset type: SYSRSn

0InitR/W1hInitialization Mode

This bit is used to keep the CAN module inactive during bit timing configuration and message RAM initialization. It is set automatically during a bus off event. Clearing this bit will not shorten the bus recovery time.

0 CAN module processes messages normally

1 CAN module ignores bus activity

Reset type: SYSRSn

22.15.2.2 CAN_ES Register (Offset = 4h) [Reset = 00000007h]

CAN_ES is shown in Figure 22-23 and described in Table 22-11.

Return to the Summary Table.

This register indicates error conditions, if any, of the CAN module. Interrupts are generated by PER, BOff and EWarn bits (if EIE bit in CAN Control Register is set) and by RxOk, TxOk, and LEC bits (if SIE bit in CAN Control Register is set). A change of bit EPass will not generate an Interrupt.

Reading the Error and Status Register clears the PER, RxOk and TxOk bits and sets the LEC to value '7'. Additionally, the Status Interrupt value (0x8000) in the Interrupt Register will be replaced by the next lower priority interrupt value.

For debug support, the auto clear functionality of Error and Status Register (clear of status flags by read) is disabled when in Debug/Suspend mode.

Figure 22-23 CAN_ES Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRESERVEDRESERVEDPER
R-0hR-0hR-0hR-0h
76543210
BOffEWarnEPassRxOkTxOkLEC
R-0hR-0hR-0hR-0hR-0hR-7h
Table 22-11 CAN_ES Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10RESERVEDR0hReserved
9RESERVEDR0hReserved
8PERR0hParity Error Detected: This bit will be reset after the CPU reads the register.

0 No parity error has been detected since last read access.

1 The parity check mechanism has detected a parity error in the Message RAM.

Reset type: SYSRSn

7BOffR0hBus-off Status Bit:

0 The CAN module is not in Bus-Off state.

1 The CAN module is in Bus-Off state.

Reset type: SYSRSn

6EWarnR0hWarning State Bit:

0 Both error counters are below the error warning limit of 96.

1 At least one of the error counters has reached the error warning limit of 96.

Reset type: SYSRSn

5EPassR0hError Passive State

0 On CAN Bus error, the CAN could send active error frames.

1 The CAN Core is in the error passive state as defined in the CAN Specification.

Reset type: SYSRSn

4RxOkR0hReception status Bit: This bit indicates the status of reception. The bit will be reset after the CPU reads the register.

0 No message has been successfully received since the last time when this bit was read by the CPU. This bit is never reset by CAN internal events.

1 A message has been successfully received since the last time when this bit was reset by a read access of the CPU. This bit will be set independent of the result of acceptance filtering.

Reset type: SYSRSn

3TxOkR0hTransmission status Bit: This bit indicates the status of transmission. The bit will be reset after the CPU reads the register.

0 No message has been successfully transmitted since the last time when this bit was read by the CPU. This bit is never reset by CAN internal events.

1 A message has been successfully transmitted (error free and acknowledged by at least one other node) since the last time when this bit was cleared by a read access of the CPU.

Reset type: SYSRSn

2-0LECR7hLast Error Code

The LEC field indicates the type of the last error on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. This field will be reset to '7' whenever the CPU reads the register.

0 No Error

1 Stuff Error: More than five equal bits in a row have been detected in a part of a received message where this is not allowed.

2 Form Error: A fixed format part of a received frame has the wrong format.

3 Ack Error: The message this CAN Core transmitted was not acknowledged by another node.

4 Bit1 Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant.

5 Bit0 Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (logical value '0'), but the monitored bus level was recessive. During Bus-Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus-Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

6 CRC Error: In a received message, the CRC check sum was incorrect. (CRC received for an incoming message does not match the calculated CRC for the received data).

7 No CAN bus event was detected since the last time when CPU has read the Error and Status Register. Any read access to the Error and Status Register re-initializes the LEC to value '7'.

Reset type: SYSRSn

22.15.2.3 CAN_ERRC Register (Offset = 8h) [Reset = 00000000h]

CAN_ERRC is shown in Figure 22-24 and described in Table 22-12.

Return to the Summary Table.

This register reflects the value of the Transmit and Receive error counters

Figure 22-24 CAN_ERRC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RPRECTEC
R-0hR-0hR-0h
Table 22-12 CAN_ERRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15RPR0hReceive Error Passive

0 The Receive Error Counter is below the error passive level.

1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification.

Reset type: SYSRSn

14-8RECR0hReceive Error Counter

Actual state of the Receive Error Counter (values from 0 to 127).

Reset type: SYSRSn

7-0TECR0hTransmit Error Counter

Actual state of the Transmit Error Counter. (values from 0 to 255).

Reset type: SYSRSn

22.15.2.4 CAN_BTR Register (Offset = Ch) [Reset = 00002301h]

CAN_BTR is shown in Figure 22-25 and described in Table 22-13.

Return to the Summary Table.

This register is used to configure the bit-timing parameters for the CAN module. This register is only writable if CCE and Init bits in the CAN Control Register are set.

The CAN bit time may be programmed in the range of 8 to 25 time quanta.

The CAN time quantum may be programmed in the range of 1 to1024 CAN_CLK periods.

Figure 22-25 CAN_BTR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBRPE
R-0hR/W-0h
15141312111098
RESERVEDTSEG2TSEG1
R-0hR/W-2hR/W-3h
76543210
SJWBRP
R/W-0hR/W-1h
Table 22-13 CAN_BTR Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16BRPER/W0hBaud Rate Prescaler Extension

Valid programmed values are 0 to 15.

By programming BRPE the Baud Rate Prescaler can be extended to values up to 1024.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

15RESERVEDR0hReserved
14-12TSEG2R/W2hTime segment after the sample point Valid programmed values are 0 to 7.

The actual TSeg2 value which is interpreted for the Bit Timing will be the programmed TSeg2 value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

11-8TSEG1R/W3hTime segment before the sample point Valid programmed values are 1 to 15.

The actual TSeg1 value interpreted for the Bit Timing will be the programmed TSeg1 value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

7-6SJWR/W0hSynchronization Jump Width Valid programmed values are 0 to 3.

The actual SJW value interpreted for the Synchronization will be the programmed SJW value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

5-0BRPR/W1hBaud Rate Prescaler-

Value by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta.

Valid programmed values are 0 to 63.

The actual BRP value interpreted for the Bit Timing will be the programmed BRP value + 1.

Note: This bit is Write Protected by CCE bit.

Reset type: SYSRSn

22.15.2.5 CAN_INT Register (Offset = 10h) [Reset = 00000000h]

CAN_INT is shown in Figure 22-26 and described in Table 22-14.

Return to the Summary Table.

This register is used to identify the source of the interrupt(s).

Figure 22-26 CAN_INT Register
313029282726252423222120191817161514131211109876543210
RESERVEDINT1IDINT0ID
R-0hR-0hR-0h
Table 22-14 CAN_INT Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16INT1IDR0hInterrupt 1 Cause

0x00 No interrupt is pending.

0x01-0x20 Number of message object (mailbox) which caused the interrupt.

0x21-0xFF Unused.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority.

Note: The CANINT1 interrupt line remains active until INT1ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. A message interrupt is cleared by clearing the mailbox's IntPnd bit. Among the message interrupts, the mailbox's interrupt priority decreases with increasing message number.

Reset type: SYSRSn

15-0INT0IDR0hInterrupt 0 Cause

0x0000 - No interrupt is pending.

0x0001 - 0x0020 - Number of message object which caused the interrupt.

0x0021 - 0x7FFF - Unused.

0x8000 - Error and Status Register value is not 0x07.

0x8001 - 0xFFFF - Unused.

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority.

Note: The CANINT0 interrupt line remains active until INT0ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. The Status Interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number.

Reset type: SYSRSn

22.15.2.6 CAN_TEST Register (Offset = 14h) [Reset = 00000000h]

CAN_TEST is shown in Figure 22-27 and described in Table 22-15.

Return to the Summary Table.

This register is used to configure the various test options supported. For all test modes, the Test bit in CAN Control Register needs to be set to one. If Test bit is set, the RDA, EXL, Tx1, Tx0, LBack and Silent bits are writable. Bit Rx monitors the state of CANRX pin and therefore is only readable. All Test Register functions are disabled when Test bit is cleared.

Note: Setting Tx[1:0] other than '00' will disturb message transfer.

Note: When the internal loop back mode is active (bit LBack is set), bit EXL will be ignored.

Figure 22-27 CAN_TEST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRDAEXL
R-0hR/W-0hR/W-0h
76543210
RXTXLBACKSILENTRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 22-15 CAN_TEST Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9RDAR/W0hRAM Direct Access Enable:

0 Normal Operation.

1 Direct access to the RAM is enabled while in Test Mode.

Reset type: SYSRSn

8EXLR/W0hExternal Loop Back Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn

7RXR0hMonitors the actual value of the CANRX pin:

0 The CAN bus is dominant.

1 The CAN bus is recessive.

Reset type: SYSRSn

6-5TXR/W0hControl of CANTX pin:

00 Normal operation, CANTX is controlled by the CAN Core.

01 Sample Point can be monitored at CANTX pin.

10 CANTX pin drives a dominant value.

11 CANTX pin drives a recessive value.

Reset type: SYSRSn

4LBACKR/W0hLoop Back Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn

3SILENTR/W0hSilent Mode:

0 Disabled.

1 Enabled.

Reset type: SYSRSn

2-0RESERVEDR0hReserved

22.15.2.7 CAN_PERR Register (Offset = 1Ch) [Reset = 00000XXXh]

CAN_PERR is shown in Figure 22-28 and described in Table 22-16.

Return to the Summary Table.

This register indicates the Word/Mailbox number where a parity error has been detected. If a parity error is detected, the PER flag will be set in the Error and Status Register. This bit is not reset by the parity check mechanism
it must be reset by reading the Error and Status Register. In addition to the PER flag, the Parity Error Code Register will indicate the memory area where the parity error has been detected. If more than one word with a parity error was detected, the highest word number with a parity error will be displayed. After a parity error has been detected, the register will hold the last error code until power is removed.

Figure 22-28 CAN_PERR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDWORD_NUMMSG_NUM
R-0hR-XR-X
Table 22-16 CAN_PERR Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0hReserved
10-8WORD_NUMRX0x01-0x05 Word number where parity error has been detected.
RDA word number (1 to 5) of the mailbox (according to the
Message RAM representation in RDA mode).

Reset type: SYSRSn

7-0MSG_NUMRX0x01-0x21 Mailbox number where parity error has been detected

Reset type: SYSRSn

22.15.2.8 CAN_RAM_INIT Register (Offset = 40h) [Reset = 00000005h]

CAN_RAM_INIT is shown in Figure 22-29 and described in Table 22-17.

Return to the Summary Table.

This register is used to initialize the Mailbox RAM. It clears the entire mailbox RAM, including the MsgVal bits.

Figure 22-29 CAN_RAM_INIT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRAM_INIT_DONECAN_RAM_INITKEY3KEY2KEY1KEY0
R-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-1h
Table 22-17 CAN_RAM_INIT Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5RAM_INIT_DONER0hCAN Mailbox RAM initialization status:

0 Read: Initialization is on-going or initialization not initiated.

1 Read: Initialization complete

Reset type: SYSRSn

4CAN_RAM_INITR/W0hInitiate CAN Mailbox RAM initialization:

0 Read: Initialization complete or initialization not initiated.
Write: No action
1 Read: Initialization is on-going
Write: Initiate CAN Mailbox RAM initialization. After initialization, this bit will be automatically cleared to 0.

Reset type: SYSRSn

3KEY3R/W0hSee Key 0

Reset type: SYSRSn

2KEY2R/W1hSee Key 0

Reset type: SYSRSn

1KEY1R/W0hSee Key 0

Reset type: SYSRSn

0KEY0R/W1hKEY3-KEY0 should be 1010 for any write to this register to be valid. These bits will be restored to their reset state after the CAN RAM initialization is complete.

Reset type: SYSRSn

22.15.2.9 CAN_GLB_INT_EN Register (Offset = 50h) [Reset = 00000000h]

CAN_GLB_INT_EN is shown in Figure 22-30 and described in Table 22-18.

Return to the Summary Table.

This register is used to enable the interrupt lines to the PIE.

Figure 22-30 CAN_GLB_INT_EN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDGLBINT1_ENGLBINT0_EN
R-0hR/W-0hR/W-0h
Table 22-18 CAN_GLB_INT_EN Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1GLBINT1_ENR/W0hGlobal Interrupt Enable for CANINT1

0 CANINT1 does not generate interrupt to PIE

1 CANINT1 generates interrupt to PIE if interrupt condition occurs

Reset type: SYSRSn

0GLBINT0_ENR/W0hGlobal Interrupt Enable for CANINT0

0 CANINT0 does not generate interrupt to PIE

1 CANINT0 generates interrupt to PIE if interrupt condition occurs

Reset type: SYSRSn

22.15.2.10 CAN_GLB_INT_FLG Register (Offset = 54h) [Reset = 00000000h]

CAN_GLB_INT_FLG is shown in Figure 22-31 and described in Table 22-19.

Return to the Summary Table.

This register indicates if and when the interrupt line to the PIE is active.

Figure 22-31 CAN_GLB_INT_FLG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT1_FLGINT0_FLG
R-0hR-0hR-0h
Table 22-19 CAN_GLB_INT_FLG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1INT1_FLGR0hCANINT1 Flag

0 No interrupt generated

1 Interrupt is generated due to CANINT1 (refer to CAN Interrupt Status Register for the condition)

Reset type: SYSRSn

0INT0_FLGR0hCANINT0 Flag

0 No interrupt generated

1 Interrupt is generated due to CANINT0 (refer to CAN Interrupt Status Register for the condition)

Reset type: SYSRSn

22.15.2.11 CAN_GLB_INT_CLR Register (Offset = 58h) [Reset = 00000000h]

CAN_GLB_INT_CLR is shown in Figure 22-32 and described in Table 22-20.

Return to the Summary Table.

This register is used to clear the interrupt to the PIE.

Figure 22-32 CAN_GLB_INT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT1_FLG_CLRINT0_FLG_CLR
R-0hW-0hW-0h
Table 22-20 CAN_GLB_INT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1INT1_FLG_CLRW0hGlobal Interrupt flag clear for CANINT1

0 No effect

1 Write 1 to clear the corresponding bit of the Global Interrupt Flag Register and allow the PIE to receive another interrupt from CANINT1.

Reset type: SYSRSn

0INT0_FLG_CLRW0hGlobal Interrupt flag clear for CANINT0

0 No effect

1 Write 1 to clear the corresponding bit of the Global Interrupt Flag Register and allow the PIE to receive another interrupt from CANINT0.

Reset type: SYSRSn

22.15.2.12 CAN_ABOTR Register (Offset = 80h) [Reset = 00000000h]

CAN_ABOTR is shown in Figure 22-33 and described in Table 22-21.

Return to the Summary Table.

This register is used to introduce a variable delay before the Bus-off recovery sequence is started.

Figure 22-33 CAN_ABOTR Register
313029282726252423222120191817161514131211109876543210
ABO_Time
R/W-0h
Table 22-21 CAN_ABOTR Register Field Descriptions
BitFieldTypeResetDescription
31-0ABO_TimeR/W0hAuto-Bus-On Timer

Number of clock cycles before a Bus-Off recovery sequence is started by clearing the Init bit. 'Clock' refers to the input clock to the CAN module. This function has to be enabled by setting bit ABO in CAN Control Register.

The Auto-Bus-On timer is realized by a 32-bit counter which starts to count down to zero when the module goes Bus-Off. The counter will be reloaded with the preload value of the ABO Time register after this phase.

NOTE: On write access to the CAN Control register while Auto-Bus-On timer is running, the Auto-Bus-On procedure will be aborted.

NOTE: During Debug mode, running Auto-Bus-On timer will be paused.

Reset type: SYSRSn

22.15.2.13 CAN_TXRQ_X Register (Offset = 84h) [Reset = 00000000h]

CAN_TXRQ_X is shown in Figure 22-34 and described in Table 22-22.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Transmission Request 21 Register (CAN_TXRQ_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the TxRqst bits of these message objects is set, the corresponding bit in this register will be set.

Figure 22-34 CAN_TXRQ_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTxRqstReg2TxRqstReg1
R-0hR-0hR-0h
Table 22-22 CAN_TXRQ_X Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2TxRqstReg2R0hTransmit Request Register 2 flag:

Bit 2 represents byte 2 of CAN_TXRQ_21. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn

1-0TxRqstReg1R0hTransmit Request Register 1 flag:

Bit 0 represents byte 0 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_TXRQ_21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

22.15.2.14 CAN_TXRQ_21 Register (Offset = 88h) [Reset = 00000000h]

CAN_TXRQ_21 is shown in Figure 22-35 and described in Table 22-23.

Return to the Summary Table.

This register holds the TxRqst bits of the mailboxes. By reading out these bits, the CPU can check for pending transmission requests. The TxRqst bit in a specific mailbox can be set/reset by the CPU via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission.

Figure 22-35 CAN_TXRQ_21 Register
313029282726252423222120191817161514131211109876543210
TxRqst
R-0h
Table 22-23 CAN_TXRQ_21 Register Field Descriptions
BitFieldTypeResetDescription
31-0TxRqstR0hTransmission Request Bits (for all message objects)

0 No transmission has been requested for this message object.

1 The transmission of this message object is requested and is not yet done.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

22.15.2.15 CAN_NDAT_X Register (Offset = 98h) [Reset = 00000000h]

CAN_NDAT_X is shown in Figure 22-36 and described in Table 22-24.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN New Data 21 Register (CAN_NDAT _21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the NewDat bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 22-36 CAN_NDAT_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDNewDatReg2NewDatReg1
R-0hR-0hR-0h
Table 22-24 CAN_NDAT_X Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2NewDatReg2R0hNew Data Register 2 flag:

Bit 2 represents byte 2 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn

1-0NewDatReg1R0hNew Data Register 1 flag:

Bit 0 represents byte 0 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_NDAT _21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

22.15.2.16 CAN_NDAT_21 Register (Offset = 9Ch) [Reset = 00000000h]

CAN_NDAT_21 is shown in Figure 22-37 and described in Table 22-25.

Return to the Summary Table.

This register holds the NewDat bits of all mailboxes. By reading out the NewDat bits, the CPU can check for which mailboxes the data portion was updated. The NewDat bit of a specific mailbox can be set/reset by the CPU via the IFx 'Message Interface' Registers or by the Message Handler after reception of a Data Frame or after a successful transmission.

Figure 22-37 CAN_NDAT_21 Register
313029282726252423222120191817161514131211109876543210
NewDat
R-0h
Table 22-25 CAN_NDAT_21 Register Field Descriptions
BitFieldTypeResetDescription
31-0NewDatR0hNew Data Bits (for all message objects)

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

22.15.2.17 CAN_IPEN_X Register (Offset = ACh) [Reset = 00000000h]

CAN_IPEN_X is shown in Figure 22-38 and described in Table 22-26.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Interrupt Pending 21 Register (CAN_IPEN_21) is set. Each bit in this register represents a group of eight mailboxes. If at least one of the IntPnd bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 22-38 CAN_IPEN_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDIntPndReg2IntPndReg1
R-0hR-0hR-0h
Table 22-26 CAN_IPEN_X Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2IntPndReg2R0hInterrupt Pending Register 2 flag:

Bit 2 represents byte 2 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn

1-0IntPndReg1R0hInterrupt Pending Register 1 flag:

Bit 0 represents byte 0 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_IPEN_21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

22.15.2.18 CAN_IPEN_21 Register (Offset = B0h) [Reset = 00000000h]

CAN_IPEN_21 is shown in Figure 22-39 and described in Table 22-27.

Return to the Summary Table.

This register holds the IntPnd bits of the mailboxes. By reading out these bits, the CPU can check for pending interrupts in the mailboxes. The IntPnd bit of a specific mailbox can be set/reset by the CPU via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission.

Figure 22-39 CAN_IPEN_21 Register
313029282726252423222120191817161514131211109876543210
IntPnd
R-0h
Table 22-27 CAN_IPEN_21 Register Field Descriptions
BitFieldTypeResetDescription
31-0IntPndR0hInterrupt Pending bits: This register contains the bits that indicate the pending interrupts in each one of the 32 mailboxes.

0 This mailbox is not the source of an interrupt.

1 This mailbox is the source of an interrupt.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

22.15.2.19 CAN_MVAL_X Register (Offset = C0h) [Reset = 00000000h]

CAN_MVAL_X is shown in Figure 22-40 and described in Table 22-28.

Return to the Summary Table.

With these bits, the CPU can detect if one or more bits in the CAN Message Valid 2_1 Register (CAN_MVAL_21) is set.Each bit in this register represents a group of eight mailboxes. If at least one of the MsgVal bits of these mailboxes are set, the corresponding bit in this register will be set.

Figure 22-40 CAN_MVAL_X Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMsgValReg2MsgValReg1
R-0hR-0hR-0h
Table 22-28 CAN_MVAL_X Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2MsgValReg2R0hMessage Valid Register 2 flag:

Bit 2 represents byte 2 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 2 will be set.

Bit 3 represents byte 3 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 3 will be set.

Reset type: SYSRSn

1-0MsgValReg1R0hMessage Valid Register 1 flag:

Bit 0 represents byte 0 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 0 will be set.

Bit 1 represents byte 1 of CAN_ MVAL _21 Register. If one or more bits in that byte are set, then bit 1 will be set.

Reset type: SYSRSn

22.15.2.20 CAN_MVAL_21 Register (Offset = C4h) [Reset = 00000000h]

CAN_MVAL_21 is shown in Figure 22-41 and described in Table 22-29.

Return to the Summary Table.

This registers hold the MsgVal bits of all mailboxes. By reading out the MsgVal bits, the CPU can check which mailbox is valid. The MsgVal bit of a specific mailbox can be set/reset by the CPU via the IF1/2 'Message Interface' Registers.

Figure 22-41 CAN_MVAL_21 Register
313029282726252423222120191817161514131211109876543210
MsgValReg
R-0h
Table 22-29 CAN_MVAL_21 Register Field Descriptions
BitFieldTypeResetDescription
31-0MsgValRegR0hMessage Valid Bits (for all message objects)

0 This message object is ignored by the message handler.

1 This message object is configured and will be considered by the message handler.

Note: Bit 0 is for mailbox 1, Bit 1 is for mailbox 2, Bit 2 is for mailbox 3,..., Bit 31 is for mailbox 32

Reset type: SYSRSn

22.15.2.21 CAN_IP_MUX21 Register (Offset = D8h) [Reset = 00000000h]

CAN_IP_MUX21 is shown in Figure 22-42 and described in Table 22-30.

Return to the Summary Table.

The IntMux bit determines for each mailbox, which of the two interrupt lines (CANINT0 or CANINT1) will be asserted when the IntPnd bit of that mailbox is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN Control Register. This will also affect the INT0ID or INT1ID flags in the Interrupt Register.

Figure 22-42 CAN_IP_MUX21 Register
313029282726252423222120191817161514131211109876543210
IntMux
R/W-0h
Table 22-30 CAN_IP_MUX21 Register Field Descriptions
BitFieldTypeResetDescription
31-0IntMuxR/W0hInterrupt Mux bits:

0 CANINT0 line is active if corresponding IntPnd flag is one.

1 CANINT1 line is active if corresponding IntPnd flag is one.

Note: Bit 0 is for mailbox 32, Bit 1 is for mailbox 1, Bit 2 is for mailbox 2,..., Bit 31 is for mailbox 31

Reset type: SYSRSn

22.15.2.22 CAN_IF1CMD Register (Offset = 100h) [Reset = 00000001h]

CAN_IF1CMD is shown in Figure 22-43 and described in Table 22-31.

Return to the Summary Table.

The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. The following points must be borne in mind while writing to this register: (1) Do not write zeros to the whole register. (2) Write to the register in a single 32-bit write or write the upper 16-bits before writing to the lower 16- bits.

Note: While Busy bit is one, IF1/IF2 Register sets are write protected.

Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.

Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message Handler may access an implemented (valid) message object instead.

Figure 22-43 CAN_IF1CMD Register
3130292827262524
RESERVED
R-0h
2322212019181716
DIRMaskArbControlClrIntPndTXRQSTDATA_ADATA_B
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BusyRESERVEDRESERVED
R-0hR/W-0hR-0h
76543210
MSG_NUM
R/W-1h
Table 22-31 CAN_IF1CMD Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23DIRR/W0hWrite/Read

0 Direction = Read: Transfer direction is from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set. That is, transfer data from the mailbox into the selected IF1/IF2 Message Buffer Registers.

1 Direction = Write: Transfer direction is from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]) . That is, transfer data from the selected IF1/IF2 Message Buffer Registers to the mailbox.

The other bits of IF1/IF2 Command Mask Register have different functions depending on the transfer direction.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22MaskR/W0hAccess Mask Bits

0 Mask bits will not be changed

1 (Direction = Read): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set.

1 (Direction = Write): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

21ArbR/W0hAccess Arbitration Bits

0 Arbitration bits will not be changed

1 (Direction = Read): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1/IF2 Register set to the mes-sage object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

20ControlR/W0hAccess control bits.

If the TxRqst/NewDat bit in this register(Bit [18]) is set, the TxRqst/NewDat bit in the IF1 message control register will be ignored.

0 Control bits will not be changed.

1 (Direction = Read): The message control bits will be transferred from the message object addressed by message number (Bits [7:0]) to the IF1 register set.

1 (Direction = Write): The message control bits will be transferred from the IF1 register set to the
message object addressed by message number (Bits [7:0]).

Note: This bit is write protected by the Busy bit.

Reset type: SYSRSn

19ClrIntPndR/W0hClear Interrupt Pending Bit

0 IntPnd bit will not be changed

1 (Direction = Read): Clears IntPnd bit in the message object.

1 (Direction = Write): This bit is ignored.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

18TXRQSTR/W0hAccess Transmission Request (TxRqst) / New Data (NewDat) Bit

0 (Direction = Read): NewDat bit will not be changed.
0 (Direction = Write): TxRqst/NewDat bit will be handled according to the Control bit.

1 (Direction = Read): Clears NewDat bit in the message object.
1 (Direction = Write): Sets TxRqst/NewDat in message object.

Note: If a CAN transmission is requested by setting TxRqst/NewDat in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in IF1/IF2 Message Control Register.

Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IF1/IF2 Message Control Register always reflect the status before resetting them.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

17DATA_AR/W0hAccess Data Bytes 0-3

0 Data Bytes 0-3 will not be changed.

1 (Direction = Read): The Data Bytes 0-3 will be transferred from the message object addressed by the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 0-3 will be transferred from the IF1/IF2 Register set to the message object addressed by the Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

16DATA_BR/W0hAccess Data Bytes 4-7

0 Data Bytes 4-7 will not be changed.

1 (Direction = Read): The Data Bytes 4-7 will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 4-7 will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

15BusyR0hBusy Flag

0 No transfer between IF1/IF2 Register Set and Message RAM is in progress.

1 Transfer between IF1/IF2 Register Set and Message RAM is in progress.

This bit is set to one after the message number has been written to bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is cleared after read/write action has been finished.

Reset type: SYSRSn

14RESERVEDR/W0hReserved
13-8RESERVEDR0hReserved
7-0MSG_NUMR/W1hNumber of message object in Message RAM which is used for data transfer

0x00 Invalid message number

0x01-0x20 Valid message numbers

0x21-0xFF Invalid message numbers

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.23 CAN_IF1MSK Register (Offset = 104h) [Reset = FFFFFFFFh]

CAN_IF1MSK is shown in Figure 22-44 and described in Table 22-32.

Return to the Summary Table.

The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 22-44 CAN_IF1MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R/W-1hR/W-1hR-1hR/W-1FFFFFFFh
2322212019181716
Msk
R/W-1FFFFFFFh
15141312111098
Msk
R/W-1FFFFFFFh
76543210
Msk
R/W-1FFFFFFFh
Table 22-32 CAN_IF1MSK Register Field Descriptions
BitFieldTypeResetDescription
31MXtdR/W1hMask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

30MDirR/W1hMask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

29RESERVEDR1hReserved
28-0MskR/W1FFFFFFFhIdentifier Mask-

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.24 CAN_IF1ARB Register (Offset = 108h) [Reset = 00000000h]

CAN_IF1ARB is shown in Figure 22-45 and described in Table 22-33.

Return to the Summary Table.

The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.

A received message is stored into the valid message object with matching identifier and Direction = receive (Data Frame) or Direction = transmit (Remote Frame).

Extended frames can be stored only in message objects with Xtd = one, standard frames in message objects with Xtd = zero.

If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it is stored into the one with the lowest message number.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 22-45 CAN_IF1ARB Register
3130292827262524
MsgValXtdDirID
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ID
R/W-0h
15141312111098
ID
R/W-0h
76543210
ID
R/W-0h
Table 22-33 CAN_IF1ARB Register Field Descriptions
BitFieldTypeResetDescription
31MsgValR/W0hMessage Valid

0 The mailbox is disabled. (The message object is ignored by the message handler).

1 The mailbox is enabled. (The message object is to be used by the message handler).

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets the Init bit in the CAN Control Register.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

30XtdR/W0hExtended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

29DirR/W0hMessage Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that frame is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28-0IDR/W0hMessage Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.25 CAN_IF1MCTL Register (Offset = 10Ch) [Reset = 00000000h]

CAN_IF1MCTL is shown in Figure 22-46 and described in Table 22-34.

Return to the Summary Table.

The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object. This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO option.

Figure 22-46 CAN_IF1MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EoBRESERVEDDLC
R/W-0hR-0hR/W-0h
Table 22-34 CAN_IF1MCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NewDatR/W0hNew Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

14MsgLstR/W0hMessage Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

13IntPndR/W0hInterrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

12UMaskR/W0hUse Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

11TxIER/W0hTransmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

10RxIER/W0hReceive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

9RmtEnR/W0hRemote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

8TxRqstR/W0hTransmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

7EoBR/W0hEnd of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

6-4RESERVEDR0hReserved
3-0DLCR/W0hData length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.26 CAN_IF1DATA Register (Offset = 110h) [Reset = 00000000h]

CAN_IF1DATA is shown in Figure 22-47 and described in Table 22-35.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 22-47 CAN_IF1DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 22-35 CAN_IF1DATA Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_3R/W0hData Byte 3

Reset type: SYSRSn

23-16Data_2R/W0hData Byte 2

Reset type: SYSRSn

15-8Data_1R/W0hData Byte 1

Reset type: SYSRSn

7-0Data_0R/W0hData Byte 0

Reset type: SYSRSn

22.15.2.27 CAN_IF1DATB Register (Offset = 114h) [Reset = 00000000h]

CAN_IF1DATB is shown in Figure 22-48 and described in Table 22-36.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 22-48 CAN_IF1DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R/W-0hR/W-0hR/W-0hR/W-0h
Table 22-36 CAN_IF1DATB Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_7R/W0hData Byte 7

Reset type: SYSRSn

23-16Data_6R/W0hData Byte 6

Reset type: SYSRSn

15-8Data_5R/W0hData Byte 5

Reset type: SYSRSn

7-0Data_4R/W0hData Byte 4

Reset type: SYSRSn

22.15.2.28 CAN_IF2CMD Register (Offset = 120h) [Reset = 00000001h]

CAN_IF2CMD is shown in Figure 22-49 and described in Table 22-37.

Return to the Summary Table.

The IF1/IF2 Command Registers configure and initiate the transfer between the IF1/IF2 Register sets and the Message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the CPU writes the message number to bits [7:0] of the IF1/IF2 Command Register. With this write operation, the Busy bit is automatically set to '1' to indicate that a transfer is in progress. After 4 to 14 clock cycles, the transfer between the Interface Register and the Message RAM will be completed and the Busy bit is cleared. The maximum number of cycles is needed when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

If the CPU writes to both IF1/IF2 Command Registers consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. The following points must be borne in mind while writing to this register: (1) Do not write zeros to the whole register. (2) Write to the register in a single 32-bit write or write the upper 16-bits before writing to the lower 16- bits.

Note: While Busy bit is one, IF1/IF2 Register sets are write protected.

Note: For debug support, the auto clear functionality of the IF1/IF2 Command Registers (clear of DMAactive flag by R/W, for devices with DMA support) is disabled during Debug/Suspend mode.

Note: If an invalid Message Number is written to bits [7:0] of the IF1/IF2 Command Register, the Message Handler may access an implemented (valid) message object instead.

Figure 22-49 CAN_IF2CMD Register
3130292827262524
RESERVED
R-0h
2322212019181716
DIRMaskArbControlClrIntPndTxRqstDATA_ADATA_B
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
BusyRESERVEDRESERVED
R-0hR/W-0hR-0h
76543210
MSG_NUM
R/W-1h
Table 22-37 CAN_IF2CMD Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23DIRR/W0hWrite/Read

0 Direction = Read: Transfer direction is from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set. That is, transfer data from the mailbox into the selected IF1/IF2 Message Buffer Registers.

1 Direction = Write: Transfer direction is from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]) . That is, transfer data from the selected IF1/IF2 Message Buffer Registers to the mailbox.

The other bits of IF1/IF2 Command Mask Register have different functions depending on the transfer direction.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22MaskR/W0hAccess Mask Bits

0 Mask bits will not be changed

1 (Direction = Read): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the IF1/IF2 Register set.

1 (Direction = Write): The Mask bits (Identifier Mask + MDir + MXtd) will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

21ArbR/W0hAccess Arbitration Bits

0 Arbitration bits will not be changed

1 (Direction = Read): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Arbitration bits (Identifier + Dir + Xtd + MsgVal) will be transferred from the IF1/IF2 Register set to the mes-sage object addressed by Message Number (Bits [7:0]).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

20ControlR/W0hAccess control bits.

If the TxRqst/NewDat bit in this register(Bit [18]) is set, the TxRqst/NewDat bit in the IF1 message control register will be ignored.

0 Control bits will not be changed.

1 (Direction = Read): The message control bits will be transferred from the message object addressed by message number (Bits [7:0]) to the IF1 register set.

1 (Direction = Write): The message control bits will be transferred from the IF1 register set to the
message object addressed by message number (Bits [7:0]).

Note: This bit is write protected by the Busy bit.

Reset type: SYSRSn

19ClrIntPndR/W0hClear Interrupt Pending Bit

0 IntPnd bit will not be changed

1 (Direction = Read): Clears IntPnd bit in the message object.

1 (Direction = Write): This bit is ignored.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

18TxRqstR/W0hAccess Transmission Request (TxRqst) / New Data (NewDat) Bit

0 (Direction = Read): NewDat bit will not be changed.
0 (Direction = Write): TxRqst/NewDat bit will be handled according to the Control bit.

1 (Direction = Read): Clears NewDat bit in the message object.
1 (Direction = Write): Sets TxRqst/NewDat in message object.

Note: If a CAN transmission is requested by setting TxRqst/NewDat in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in IF1/IF2 Message Control Register.

Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IF1/IF2 Message Control Register always reflect the status before resetting them.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

17DATA_AR/W0hAccess Data Bytes 0-3

0 Data Bytes 0-3 will not be changed.

1 (Direction = Read): The Data Bytes 0-3 will be transferred from the message object addressed by the Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 0-3 will be transferred from the IF1/IF2 Register set to the message object addressed by the Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

16DATA_BR/W0hAccess Data Bytes 4-7

0 Data Bytes 4-7 will not be changed.

1 (Direction = Read): The Data Bytes 4-7 will be transferred from the message object addressed by Message Number (Bits [7:0]) to the corresponding IF1/IF2 Register set.

1 (Direction = Write): The Data Bytes 4-7 will be transferred from the IF1/IF2 Register set to the message object addressed by Message Number (Bits [7:0]).

Note: The duration of the message transfer is independent of the number of bytes to be transferred.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

15BusyR0hBusy Flag

0 No transfer between IF1/IF2 Register Set and Message RAM is in progress.

1 Transfer between IF1/IF2 Register Set and Message RAM is in progress.

This bit is set to one after the message number has been written to bits [7:0]. IF1/IF2 Register Set will be write protected. The bit is cleared after read/write action has been finished.

Reset type: SYSRSn

14RESERVEDR/W0hReserved
13-8RESERVEDR0hReserved
7-0MSG_NUMR/W1hNumber of message object in Message RAM which is used for data transfer

0x00 Invalid message number

0x01-0x20 Valid message numbers

0x21-0xFF Invalid message numbers

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.29 CAN_IF2MSK Register (Offset = 124h) [Reset = FFFFFFFFh]

CAN_IF2MSK is shown in Figure 22-50 and described in Table 22-38.

Return to the Summary Table.

The bits of the IF1/IF2 Mask Registers mirror the mask bits of a message object.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 22-50 CAN_IF2MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R/W-1hR/W-1hR-1hR/W-1FFFFFFFh
2322212019181716
Msk
R/W-1FFFFFFFh
15141312111098
Msk
R/W-1FFFFFFFh
76543210
Msk
R/W-1FFFFFFFh
Table 22-38 CAN_IF2MSK Register Field Descriptions
BitFieldTypeResetDescription
31MXtdR/W1hMask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

30MDirR/W1hMask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

29RESERVEDR1hReserved
28-0MskR/W1FFFFFFFhIdentifier Mask

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.30 CAN_IF2ARB Register (Offset = 128h) [Reset = 00000000h]

CAN_IF2ARB is shown in Figure 22-51 and described in Table 22-39.

Return to the Summary Table.

The bits of the IF1/IF2 Arbitration Registers mirror the arbitration bits of a message object. The Arbitration bits ID[28:0], Xtd, and Dir are used to define the identifier and type of outgoing messages and (together with the Mask bits Msk[28:0], MXtd, and MDir) for acceptance filtering of incoming messages.

A received message is stored into the valid message object with matching identifier and Direction = receive (Data Frame) or Direction = transmit (Remote Frame).

Extended frames can be stored only in message objects with Xtd = one, standard frames in message objects with Xtd = zero.

If a received message (Data Frame or Remote Frame) matches more than one valid message objects, it is stored into the one with the lowest message number.

Note: While Busy bit of IF1/IF2 Command Register is one, IF1/IF2 Register Set is write-protected.

Figure 22-51 CAN_IF2ARB Register
3130292827262524
MsgValXtdDirID
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ID
R/W-0h
15141312111098
ID
R/W-0h
76543210
ID
R/W-0h
Table 22-39 CAN_IF2ARB Register Field Descriptions
BitFieldTypeResetDescription
31MsgValR/W0hMessage Valid

0 The mailbox is disabled. (The message object is ignored by the message handler).

1 The mailbox is enabled. (The message object is to be used by the message handler).

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets the Init bit in the CAN Control Register.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

30XtdR/W0hExtended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

29DirR/W0hMessage Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that frame is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

28-0IDR/W0hMessage Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.31 CAN_IF2MCTL Register (Offset = 12Ch) [Reset = 00000000h]

CAN_IF2MCTL is shown in Figure 22-52 and described in Table 22-40.

Return to the Summary Table.

The bits of the IF1/IF2 Message Control Registers mirror the message control bits of a message object. This register has control/status bits pertaining to interrupts, acceptance mask, remote frames and FIFO option.

Figure 22-52 CAN_IF2MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EoBRESERVEDDLC
R/W-0hR-0hR/W-0h
Table 22-40 CAN_IF2MCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NewDatR/W0hNew Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

14MsgLstR/W0hMessage Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

13IntPndR/W0hInterrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

12UMaskR/W0hUse Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

11TxIER/W0hTransmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

10RxIER/W0hReceive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

9RmtEnR/W0hRemote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

8TxRqstR/W0hTransmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

7EoBR/W0hEnd of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

6-4RESERVEDR0hReserved
3-0DLCR/W0hData length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Note: This bit is write protected by Busy bit.

Reset type: SYSRSn

22.15.2.32 CAN_IF2DATA Register (Offset = 130h) [Reset = 00000000h]

CAN_IF2DATA is shown in Figure 22-53 and described in Table 22-41.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 22-53 CAN_IF2DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 22-41 CAN_IF2DATA Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_3R/W0hData Byte 3

Reset type: SYSRSn

23-16Data_2R/W0hData Byte 2

Reset type: SYSRSn

15-8Data_1R/W0hData Byte 1

Reset type: SYSRSn

7-0Data_0R/W0hData Byte 0

Reset type: SYSRSn

22.15.2.33 CAN_IF2DATB Register (Offset = 134h) [Reset = 00000000h]

CAN_IF2DATB is shown in Figure 22-54 and described in Table 22-42.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message. The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order. In a CAN Data Frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. All bits in this register are write-protected by the Busy bit.

Figure 22-54 CAN_IF2DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R/W-0hR/W-0hR/W-0hR/W-0h
Table 22-42 CAN_IF2DATB Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_7R/W0hData Byte 7

Reset type: SYSRSn

23-16Data_6R/W0hData Byte 6

Reset type: SYSRSn

15-8Data_5R/W0hData Byte 5

Reset type: SYSRSn

7-0Data_4R/W0hData Byte 4

Reset type: SYSRSn

22.15.2.34 CAN_IF3OBS Register (Offset = 140h) [Reset = 00000000h]

CAN_IF3OBS is shown in Figure 22-55 and described in Table 22-43.

Return to the Summary Table.

The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from Message RAM by CPU.

The observation flags (Bits [4:0]) in the IF3 Observation register are used to determine, which data sections of the IF3 Interface Register set have to be read in order to complete a DMA read cycle. After all marked data sections are read, the DCAN is enabled to update the IF3 Interface Register set with new data.

Any access order of single bytes or half-words is supported. When using byte or half-word accesses, a data section is marked as completed, if all bytes are read.

Note: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses.

A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables updating of IF3 Interface Register set with new data. To avoid data inconsistency, the DMA controller should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can be observed via status flags (Bits [12:8]).

With this, the observation status bits and the IF3Upd bit could be used by the application to realize the notification about new IF3 content in polling or interrupt mode

Figure 22-55 CAN_IF3OBS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
IF3UpdRESERVEDIF3SDBIF3SDAIF3SCIF3SAIF3SM
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDData_BData_ACtrlArbMask
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 22-43 CAN_IF3OBS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15IF3UpdR0hIF3 Update Data

0 No new data has been loaded since last IF3 read.

1 New data has been loaded since last IF3 read.

Reset type: SYSRSn

14-13RESERVEDR0hReserved
12IF3SDBR0hIF3 Status of Data B read access

0 All Data B bytes are already read out, or are not marked to be read.

1 Data B section has still data to be read out.

Reset type: SYSRSn

11IF3SDAR0hIF3 Status of Data A read access

0 All Data A bytes are already read out, or are not marked to be read.

1 Data A section has still data to be read out.

Reset type: SYSRSn

10IF3SCR0hIF3 Status of Control bits read access

0 All Control section bytes are already read out, or are not marked to be read.

1 Control section has still data to be read out.

Reset type: SYSRSn

9IF3SAR0hIF3 Status of Arbitration data read access

0 All Arbitration data bytes are already read out, or are not marked to be read.

1 Arbitration section has still data to be read out.

Reset type: SYSRSn

8IF3SMR0hIF3 Status of Mask data read access

0 All Mask data bytes are already read out, or are not marked to be read.

1 Mask section has still data to be read out.

Reset type: SYSRSn

7-5RESERVEDR0hReserved
4Data_BR/W0hData B read observation

0 Data B section not to be read.

1 Data B section has to be read to enable next IF3 update.

Reset type: SYSRSn

3Data_AR/W0hData A read observation

0 Data A section not to be read.

1 Data A section has to be read to enable next IF3 update.

Reset type: SYSRSn

2CtrlR/W0hCtrl read observation

0 Ctrl section not to be read.

1 Ctrl section has to be read to enable next IF3 update.

Reset type: SYSRSn

1ArbR/W0hArbitration data read observation

0 Arbitration data not to be read.

1 Arbitration data has to be read to enable next IF3 update.

Reset type: SYSRSn

0MaskR/W0hMask data read observation

0 Mask data not to be read.

1 Mask data has to be read to enable next IF3 update.

Reset type: SYSRSn

22.15.2.35 CAN_IF3MSK Register (Offset = 144h) [Reset = FFFFFFFFh]

CAN_IF3MSK is shown in Figure 22-56 and described in Table 22-44.

Return to the Summary Table.

This register provides a window to the acceptance mask for the chosen mailbox.

Figure 22-56 CAN_IF3MSK Register
3130292827262524
MXtdMDirRESERVEDMsk
R-1hR-1hR-1hR-1FFFFFFFh
2322212019181716
Msk
R-1FFFFFFFh
15141312111098
Msk
R-1FFFFFFFh
76543210
Msk
R-1FFFFFFFh
Table 22-44 CAN_IF3MSK Register Field Descriptions
BitFieldTypeResetDescription
31MXtdR1hMask Extended Identifier

0 The extended identifier bit (Xtd) has no effect on the acceptance filtering.

1 The extended identifier bit (Xtd) is used for acceptance filtering.

Note: When 11-bit ('standard') identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered.

Reset type: SYSRSn

30MDirR1hMask Message Direction

0 The message direction bit (Dir) has no effect on the acceptance filtering.

1 The message direction bit (Dir) is used for acceptance filtering.

Reset type: SYSRSn

29RESERVEDR1hReserved
28-0MskR1FFFFFFFhIdentifier Mask Identifier Mask

0 The corresponding bit in the identifier of the message object is not used for acceptance filtering (don't care).

1 The corresponding bit in the identifier of the message object is used for acceptance filtering. Identifier Mask

Reset type: SYSRSn

22.15.2.36 CAN_IF3ARB Register (Offset = 148h) [Reset = 00000000h]

CAN_IF3ARB is shown in Figure 22-57 and described in Table 22-45.

Return to the Summary Table.

The bits of the IF3 Arbitration Register mirrors the arbitration bits of a message object.

Figure 22-57 CAN_IF3ARB Register
3130292827262524
MsgValXtdDirID
R-0hR-0hR-0hR-0h
2322212019181716
ID
R-0h
15141312111098
ID
R-0h
76543210
ID
R-0h
Table 22-45 CAN_IF3ARB Register Field Descriptions
BitFieldTypeResetDescription
31MsgValR0hMessage Valid

0 The message object is ignored by the message handler.

1 The message object is to be used by the message handler.

The CPU should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init in the CAN Control Register.

Reset type: SYSRSn

30XtdR0hExtended Identifier

0 The 11-bit ('standard') Identifier is used for this message object.

1 The 29-bit ('extended') Identifier is used for this message object.

Reset type: SYSRSn

29DirR0hMessage Direction

0 Direction = receive: On TxRqst, a remote frame with the identifier of this message object is transmitted. On reception of a data frame with matching identifier, that message is stored in this message object.

1 Direction = transmit: On TxRqst, the respective message object is transmitted as a data frame. On reception of a remote frame with matching identifier, the TxRqst bit of this message object is set (if RmtEn = one).

Reset type: SYSRSn

28-0IDR0hMessage Identifier

ID[28:0] 29-bit Identifier ('Extended Frame')

ID[28:18] 11-bit Identifier ('Standard Frame')

Reset type: SYSRSn

22.15.2.37 CAN_IF3MCTL Register (Offset = 14Ch) [Reset = 00000000h]

CAN_IF3MCTL is shown in Figure 22-58 and described in Table 22-46.

Return to the Summary Table.

The bits of the IF3 Message Control Register mirrors the message control bits of a message object.

Figure 22-58 CAN_IF3MCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
NewDatMsgLstIntPndUMaskTxIERxIERmtEnTxRqst
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
EoBRESERVEDDLC
R-0hR-0hR-0h
Table 22-46 CAN_IF3MCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15NewDatR0hNew Data

0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU.

1 The message handler or the CPU has written new data into the data portion of this message object.

Reset type: SYSRSn

14MsgLstR0hMessage Lost (only valid for message objects with direction = receive)

0 No message lost since the last time when this bit was reset by the CPU.

1 The message handler stored a new message into this object when NewDat was still set, so the previous message has been overwritten.

Reset type: SYSRSn

13IntPndR0hInterrupt Pending

0 This message object is not the source of an interrupt.

1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.

Reset type: SYSRSn

12UMaskR0hUse Acceptance Mask

0 Mask ignored

1 Use Mask (Msk[28:0], MXtd, and MDir) for acceptance filtering

If the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one.

Reset type: SYSRSn

11TxIER0hTransmit Interrupt Enable

0 IntPnd will not be triggered after the successful transmission of a frame.

1 IntPnd will be triggered after the successful transmission of a frame.

Reset type: SYSRSn

10RxIER0hReceive Interrupt Enable

0 IntPnd will not be triggered after the successful reception of a frame.

1 IntPnd will be triggered after the successful reception of a frame.

Reset type: SYSRSn

9RmtEnR0hRemote Enable

0 At the reception of a remote frame, TxRqst is not changed.

1 At the reception of a remote frame, TxRqst is set.

Reset type: SYSRSn

8TxRqstR0hTransmit Request

0 This message object is not waiting for a transmission.

1 The transmission of this message object is requested and is not yet done.

Reset type: SYSRSn

7EoBR0hEnd of Block

0 The message object is part of a FIFO Buffer block and is not the last message object of the FIFO Buffer block.

1 The message object is a single message object or the last message object in a FIFO Buffer Block.

Note: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one.

Reset type: SYSRSn

6-4RESERVEDR0hReserved
3-0DLCR0hData length code

0-8 Data frame has 0-8 data bytes.

9-15 Data frame has 8 data bytes.

Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message.

Reset type: SYSRSn

22.15.2.38 CAN_IF3DATA Register (Offset = 150h) [Reset = 00000000h]

CAN_IF3DATA is shown in Figure 22-59 and described in Table 22-47.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message.

Figure 22-59 CAN_IF3DATA Register
313029282726252423222120191817161514131211109876543210
Data_3Data_2Data_1Data_0
R-0hR-0hR-0hR-0h
Table 22-47 CAN_IF3DATA Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_3R0hData Byte 3

Reset type: SYSRSn

23-16Data_2R0hData Byte 2

Reset type: SYSRSn

15-8Data_1R0hData Byte 1

Reset type: SYSRSn

7-0Data_0R0hData Byte 0

Reset type: SYSRSn

22.15.2.39 CAN_IF3DATB Register (Offset = 154h) [Reset = 00000000h]

CAN_IF3DATB is shown in Figure 22-60 and described in Table 22-48.

Return to the Summary Table.

This register provides a window to the data bytes of the CAN message.

Figure 22-60 CAN_IF3DATB Register
313029282726252423222120191817161514131211109876543210
Data_7Data_6Data_5Data_4
R-0hR-0hR-0hR-0h
Table 22-48 CAN_IF3DATB Register Field Descriptions
BitFieldTypeResetDescription
31-24Data_7R0hData Byte 7

Reset type: SYSRSn

23-16Data_6R0hData Byte 6

Reset type: SYSRSn

15-8Data_5R0hData Byte 5

Reset type: SYSRSn

7-0Data_4R0hData Byte 4

Reset type: SYSRSn

22.15.2.40 CAN_IF3UPD Register (Offset = 160h) [Reset = 00000000h]

CAN_IF3UPD is shown in Figure 22-61 and described in Table 22-49.

Return to the Summary Table.

The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UpdEn flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set. Note: IF3 Update enable should not be set for transmit objects.

Figure 22-61 CAN_IF3UPD Register
313029282726252423222120191817161514131211109876543210
IF3UpdEn
R/W-0h
Table 22-49 CAN_IF3UPD Register Field Descriptions
BitFieldTypeResetDescription
31-0IF3UpdEnR/W0hIF3 Update Enabled (for all message objects)

0 Automatic IF3 update is disabled for this message object.

1 Automatic IF3 update is enabled for this message object. A message object is scheduled to be copied to IF3 register set, if NewDat flag of the message object is active.

Reset type: SYSRSn