SPRUHM8K December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
Table 3-312 lists the memory-mapped registers for the FLASH_CTRL_REGS registers. All register offset addresses not listed in Table 3-312 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | FRDCNTL | Flash Read Control Register | EALLOW | Go |
1Eh | FBAC | Flash Bank Access Control Register | EALLOW | Go |
20h | FBFALLBACK | Flash Bank Fallback Power Register | EALLOW | Go |
22h | FBPRDY | Flash Bank Pump Ready Register | EALLOW | Go |
24h | FPAC1 | Flash Pump Access Control Register 1 | EALLOW | Go |
2Ah | FMSTAT | Flash Module Status Register | EALLOW | Go |
180h | FRD_INTF_CTRL | Flash Read Interface Control Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-313 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
FRDCNTL is shown in Figure 3-279 and described in Table 3-314.
Return to the Summary Table.
Flash Read Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RWAIT | RESERVED | |||||||||||||
R-0h | R/W-Fh | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | RWAIT | R/W | Fh | Random read waitstate These bits indicate how many waitstates are added to a flash read/fetch access. The RWAIT value can be set anywhere from 0 to 0xF. For a flash access, data is returned in RWAIT+1 SYSCLK cycles. Note: The required wait states for each SYSCLK frequency can be found in the device data manual. Reset type: SYSRSn |
7-0 | RESERVED | R | 0h | Reserved |
FBAC is shown in Figure 3-280 and described in Table 3-315.
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Flash Bank Access Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | VREADST | |||||||||||||||||||||||||||||
R-0h | R/W-0h | R/W-Fh | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R/W | 0h | Reserved |
7-0 | VREADST | R/W | Fh | This bit-field ensures that the requisite delay is introduced for the flash pump/bank to come out of low-power mode, so that the flash/OTP array is ready for CPU accesses. Recommended configuration: 0xF (reset value) - If SYSCLK=10MHz (INTOSC) 0x14 - If SYSCLK > 10MHz Before entering any low-power mode for the flash bank/pump, this bit must be configured as described in the 'Flash and OTP Memory' chapter of the TRM. Applications typically use the flash bank/pump low-power modes to reduce power for following reasons: (i) during the device-level low-power modes such as IDLE/STANDBY/HALT (ii) while running code off RAM after powering down the flash. Reset type: SYSRSn |
FBFALLBACK is shown in Figure 3-281 and described in Table 3-316.
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Flash Bank Fallback Power Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BNKPWR0 | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1-0 | BNKPWR0 | R/W | 0h | Bank Power Mode Control 00 Sleep (Sense amplifiers and sense reference disabled) 01 Standby (Sense amplifiers disabled, but sense reference enabled) 10 Reserved 11 Active (Both sense amplifiers and sense reference enabled) Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. Reset type: SYSRSn |
FBPRDY is shown in Figure 3-282 and described in Table 3-317.
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Flash Bank Pump Ready Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PUMPRDY | RESERVED | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BANKRDY | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | PUMPRDY | R | 0h | Pump Ready. This is a read-only bit which allows software to determine if the pump is ready for flash access before attempting the actual access. If an access is made to a bank when the pump is not ready, wait states are asserted until it becomes ready. 0 Pump is not ready. 1 Pump is ready, in active power state. Reset type: SYSRSn |
14-1 | RESERVED | R | 0h | Reserved |
0 | BANKRDY | R | 0h | Bank Ready. This is a read-only register which allows software to determine if the bank is ready for Flash access before the access is attempted. Note: The user should wait for both the pump and the bank to be ready before attempting an access. 0 Bank is not ready. 1 Bank is in active power mode and is ready for access. Reset type: SYSRSn |
FPAC1 is shown in Figure 3-283 and described in Table 3-318.
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Flash Pump Access Control Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PSLEEP | ||||||
R-0h | R/W-860h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
PSLEEP | |||||||
R/W-860h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PMPPWR | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-16 | PSLEEP | R/W | 860h | Pump sleep. These bits contain the starting count value for the charge pump sleep down counter. While the charge pump is in sleep mode, the power mode management logic holds the charge pump sleep counter at this value. When the charge pump exits sleep power mode, the down counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles before putting the charge pump into active power mode. Note: The pump sleep down counter uses a prescaled clock which is divided by 2 of input SYSCLK. The configured PSLEEP value should yield a delay of at least 20 microseconds for the pump to go to active mode. Reset type: SYSRSn |
15-1 | RESERVED | R | 0h | Reserved |
0 | PMPPWR | R/W | 0h | Flash Charge Pump Control Power Mode. Configures the power mode of the charge pump. 0 Sleep (all pump circuits disabled) 1 Active (all pump circuits active) Reset type: SYSRSn |
FMSTAT is shown in Figure 3-284 and described in Table 3-319.
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Flash Module Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R-0h | R-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | PGV | RESERVED | EV | RESERVED | BUSY |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERS | PGM | INVDAT | CSTAT | VOLTSTAT | ESUSP | PSUSP | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R | 0h | Reserved |
16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | PGV | R | 0h | Program verify When set, indicates that a word is not successfully programmed after the maximum allowed number of program pulses are given for program operation. Reset type: SYSRSn |
11 | RESERVED | R | 0h | Reserved |
10 | EV | R | 0h | Erase verify When set, indicates that a sector is not successfully erased after the maximum allowed number of erase pulses are given for erase operation. Reset type: SYSRSn |
9 | RESERVED | R | 0h | Reserved |
8 | BUSY | R | 0h | When set, this bit indicates that a program, erase, or suspend operation is being processed. Reset type: SYSRSn |
7 | ERS | R | 0h | Erase Active. When set, this bit indicates that the flash module is actively performing an erase operation. This bit is set when erasing starts and is cleared when erasing is complete. It is also cleared when the erase is suspended and set when the erase resumes. Reset type: SYSRSn |
6 | PGM | R | 0h | Program Active. When set, this bit indicates that the flash module is currently performing a program operation. This bit is set when programming starts and is cleared when programming is complete. It is also cleared when programming is suspended and set when programming is resumed. Reset type: SYSRSn |
5 | INVDAT | R | 0h | Invalid Data. When set, this bit indicates that the user attempted to program a '1' where a '0' was already present. Reset type: SYSRSn |
4 | CSTAT | R | 0h | Command Status. Once the FSM starts any failure will set this bit. When set, this bit informs the host that the program, erase, or validate sector command failed and the command was stopped. This bit is cleared by the Clear Status command. For some errors, this will be the only indication of an FSM error because the cause does not fall within the other error bit types. Reset type: SYSRSn |
3 | VOLTSTAT | R | 0h | Core Voltage Status. When set, this bit indicates that the core voltage generator of the pump power upply dipped below the lower limit allowable during a program or erase operation. Reset type: SYSRSn |
2 | ESUSP | R | 0h | When set, this bit indicates that the flash module has received and processed an erase suspend operation. This bit remains set until the erase resume command has been issued or until the Clear_More command is run. Reset type: SYSRSn |
1 | PSUSP | R | 0h | When set, this bit indicates that the flash module has received and processed a program suspend operation. This bit remains set until the program resume command has been issued or until the Clear_More command is run. Reset type: SYSRSn |
0 | RESERVED | R | 0h | Reserved |
FRD_INTF_CTRL is shown in Figure 3-285 and described in Table 3-320.
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Flash Read Interface Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DATA_CACHE_EN | PREFETCH_EN | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-2 | RESERVED | R | 0h | Reserved |
1 | DATA_CACHE_EN | R/W | 0h | Data cache enable. 0 A value of 0 disables the data cache. 1 A value of 1 enables the data cache. Reset type: SYSRSn |
0 | PREFETCH_EN | R/W | 0h | Prefetch enable. 0 A value of 0 disables prefetch mechanism. 1 A value of 1 enables pre-fetch mechanism. Reset type: SYSRSn |