SPRUHM8K December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
Table 3-176 lists the memory-mapped registers for the CPU_SYS_REGS registers. All register offset addresses not listed in Table 3-176 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | CPUSYSLOCK1 | Lock bit for CPUSYS registers | EALLOW | Go |
6h | HIBBOOTMODE | HIB Boot Mode Register | EALLOW | Go |
8h | IORESTOREADDR | IORestore() routine Address Register | EALLOW | Go |
Ah | PIEVERRADDR | PIE Vector Fetch Error Address register | EALLOW | Go |
22h | PCLKCR0 | Peripheral Clock Gating Registers | EALLOW | Go |
24h | PCLKCR1 | Peripheral Clock Gating Registers | EALLOW | Go |
26h | PCLKCR2 | Peripheral Clock Gating Registers | EALLOW | Go |
28h | PCLKCR3 | Peripheral Clock Gating Registers | EALLOW | Go |
2Ah | PCLKCR4 | Peripheral Clock Gating Registers | EALLOW | Go |
2Eh | PCLKCR6 | Peripheral Clock Gating Registers | EALLOW | Go |
30h | PCLKCR7 | Peripheral Clock Gating Registers | EALLOW | Go |
32h | PCLKCR8 | Peripheral Clock Gating Registers | EALLOW | Go |
34h | PCLKCR9 | Peripheral Clock Gating Registers | EALLOW | Go |
36h | PCLKCR10 | Peripheral Clock Gating Registers | EALLOW | Go |
38h | PCLKCR11 | Peripheral Clock Gating Registers | EALLOW | Go |
3Ah | PCLKCR12 | Peripheral Clock Gating Registers | EALLOW | Go |
3Ch | PCLKCR13 | Peripheral Clock Gating Registers | EALLOW | Go |
3Eh | PCLKCR14 | Peripheral Clock Gating Registers | EALLOW | Go |
42h | PCLKCR16 | Peripheral Clock Gating Registers | EALLOW | Go |
74h | SECMSEL | Secondary Master Select register for common peripherals: Selects between CLA & DMA | EALLOW | Go |
76h | LPMCR | LPM Control Register | EALLOW | Go |
78h | GPIOLPMSEL0 | GPIO LPM Wakeup select registers | EALLOW | Go |
7Ah | GPIOLPMSEL1 | GPIO LPM Wakeup select registers | EALLOW | Go |
7Ch | TMR2CLKCTL | Timer2 Clock Measurement functionality control register | EALLOW | Go |
80h | RESC | Reset Cause register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-177 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CPUSYSLOCK1 is shown in Figure 3-161 and described in Table 3-178.
Return to the Summary Table.
Lock bit for CPUSYS registers
Notes:
[1] Any bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect
[2] The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIOLPMSEL1 | GPIOLPMSEL0 | LPMCR | SECMSEL | PCLKCR16 | PCLKCR15 | PCLKCR14 | PCLKCR13 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PCLKCR12 | PCLKCR11 | PCLKCR10 | PCLKCR9 | PCLKCR8 | PCLKCR7 | PCLKCR6 | PCLKCR5 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PCLKCR4 | PCLKCR3 | PCLKCR2 | PCLKCR1 | PCLKCR0 | PIEVERRADDR | IORESTOREADDR | HIBBOOTMODE |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R-0 | 0h | Reserved |
23 | GPIOLPMSEL1 | R/WSonce | 0h | Lock bit for GPIOLPMSEL1 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
22 | GPIOLPMSEL0 | R/WSonce | 0h | Lock bit for GPIOLPMSEL0 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
21 | LPMCR | R/WSonce | 0h | Lock bit for LPMCR Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
20 | SECMSEL | R/WSonce | 0h | Lock bit for SECMSEL Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
19 | PCLKCR16 | R/WSonce | 0h | Lock bit for PCLKCR16 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
18 | PCLKCR15 | R/WSonce | 0h | Lock bit for PCLKCR15 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
17 | PCLKCR14 | R/WSonce | 0h | Lock bit for PCLKCR14 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
16 | PCLKCR13 | R/WSonce | 0h | Lock bit for PCLKCR13 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
15 | PCLKCR12 | R/WSonce | 0h | Lock bit for PCLKCR12 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
14 | PCLKCR11 | R/WSonce | 0h | Lock bit for PCLKCR11 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
13 | PCLKCR10 | R/WSonce | 0h | Lock bit for PCLKCR10 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
12 | PCLKCR9 | R/WSonce | 0h | Lock bit for PCLKCR9 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
11 | PCLKCR8 | R/WSonce | 0h | Lock bit for PCLKCR8 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
10 | PCLKCR7 | R/WSonce | 0h | Lock bit for PCLKCR7 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
9 | PCLKCR6 | R/WSonce | 0h | Lock bit for PCLKCR6 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
8 | PCLKCR5 | R/WSonce | 0h | Lock bit for PCLKCR5 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
7 | PCLKCR4 | R/WSonce | 0h | Lock bit for PCLKCR4 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
6 | PCLKCR3 | R/WSonce | 0h | Lock bit for PCLKCR3 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
5 | PCLKCR2 | R/WSonce | 0h | Lock bit for PCLKCR2 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
4 | PCLKCR1 | R/WSonce | 0h | Lock bit for PCLKCR1 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
3 | PCLKCR0 | R/WSonce | 0h | Lock bit for PCLKCR0 Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
2 | PIEVERRADDR | R/WSonce | 0h | Lock bit for PIEVERRADDR Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
1 | IORESTOREADDR | R/WSonce | 0h | Lock bit for IORESTOREADDR Register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
0 | HIBBOOTMODE | R/WSonce | 0h | Lock bit for HIBBOOTMODE register: 0: Respective register is not locked 1: Respective register is locked. Reset type: SYSRSn |
HIBBOOTMODE is shown in Figure 3-162 and described in Table 3-179.
Return to the Summary Table.
HIB Boot Mode Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BMODE | |||||||||||||||||||||||||||||||
R/W-Fh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BMODE | R/W | Fh | This register defined the boot mode on a HIB Wakeup. Its the responsibility of user to initialize the appropriate boot mode before going into HIB mode. Refer to the Boot ROM section for more details on this register Reset type: POR |
IORESTOREADDR is shown in Figure 3-163 and described in Table 3-180.
Return to the Summary Table.
IORestore() routine Address Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||||||||||||||||||||||||||
R-0-0h | R/W-003FFFFFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-0 | ADDR | R/W | 003FFFFFh | This register defines the address of the restoreIO() routine on a HIB wakeup. Its the responsibility of user to initialize this register with the restoreIO() routine address before going into HIB mode. Refer to the Boot ROM section for more details on this register. Reset type: POR |
PIEVERRADDR is shown in Figure 3-164 and described in Table 3-181.
Return to the Summary Table.
PIE Vector Fetch Error Address register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADDR | ||||||||||||||||||||||||||||||
R-0-0h | R/W-003FFFFFh | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-0 | ADDR | R/W | 003FFFFFh | This register defines the address of the PIE Vector Fetch Error handler routine. Its the responsibility of user to initialize this register. If this register is not initialized, a default error handler at address 0x3fffbe will get executed. Refer to the Boot ROM section for more details on this register. Reset type: XRSn |
PCLKCR0 is shown in Figure 3-165 and described in Table 3-182.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | GTBCLKSYNC | TBCLKSYNC | RESERVED | HRPWM | |||
R-0-0h | R/W-0h | R/W-0h | R-0-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUTIMER2 | CPUTIMER1 | CPUTIMER0 | DMA | RESERVED | CLA1 | |
R-0-0h | R/W-1h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | GTBCLKSYNC | R/W | 0h | EPWM Time Base Clock Global sync: When set by CPU1, PWM time bases of all modules start counting. The effect of this bit is seen on all the EPMW modules irrespective of their partitioning based on CPUSEL Notes: 1. This bit on the CPU2.PCLKCR0 register has no effect. 2. Writing '1' to this bit overrides the effect of write '1' to the TBCLKSYNC bit at the same time Reset type: SYSRSn |
18 | TBCLKSYNC | R/W | 0h | EPWM Time Base Clock sync: When set PWM time bases of all the PWM modules belonging to the same CPU-Subsystem (as partitioned using their CPUSEL bits) start counting. This bit only impacts the TBCTR of all EPWM modules. Everything except the TBCTR of each module enabled in PCLKCR2 will still be clocked by EPWMCLK. Notes: 1. This bit from CPU1.PCLKCR0 or CPU2.PCLKCR0 is selected and fed to the individual EPWM modules based on their respective CPUSEL bit. Reset type: SYSRSn |
17 | RESERVED | R-0 | 0h | Reserved |
16 | HRPWM | R/W | 0h | HRPWM Clock Enable Bit: When set, this enables the clock to the HRPWM module 1: HRPWM clock is enabled 0: HRPWM clock is disabled Note: [1] This bit is present only in CPU1.PCLKCR0. This bit is not used (R/W) in CPU2.PCLKCR0 Reset type: SYSRSn |
15-6 | RESERVED | R-0 | 0h | Reserved |
5 | CPUTIMER2 | R/W | 1h | CPUTIMER2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | CPUTIMER1 | R/W | 1h | CPUTIMER1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | CPUTIMER0 | R/W | 1h | CPUTIMER0 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | DMA | R/W | 0h | DMA Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | CLA1 | R/W | 0h | CLA1 Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR1 is shown in Figure 3-166 and described in Table 3-183.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EMIF2 | EMIF1 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | EMIF2 | R/W | 0h | EMIF2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] These bits are not used (R/W) in CPU2.PCLKCR1 register. EMIF1 & EMIF2 clock enabled are controlled only from CPU1.PCLKCR1 register. Reset type: SYSRSn |
0 | EMIF1 | R/W | 0h | EMIF1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] These bits are not used (R/W) in CPU2.PCLKCR1 register. EMIF1 & EMIF2 clock enabled are controlled only from CPU1.PCLKCR1 register. Reset type: SYSRSn |
PCLKCR2 is shown in Figure 3-167 and described in Table 3-184.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | EPWM12 | EPWM11 | EPWM10 | EPWM9 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM8 | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | EPWM12 | R/W | 0h | EPWM12 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
10 | EPWM11 | R/W | 0h | EPWM11 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
9 | EPWM10 | R/W | 0h | EPWM10 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
8 | EPWM9 | R/W | 0h | EPWM9 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
7 | EPWM8 | R/W | 0h | EPWM8 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
6 | EPWM7 | R/W | 0h | EPWM7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | EPWM6 | R/W | 0h | EPWM6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | EPWM5 | R/W | 0h | EPWM5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | EPWM4 | R/W | 0h | EPWM4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] This bit is also used to enable clocking for CLB4 Reset type: SYSRSn |
2 | EPWM3 | R/W | 0h | EPWM3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] This bit is also used to enable clocking for CLB3 Reset type: SYSRSn |
1 | EPWM2 | R/W | 0h | EPWM2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] This bit is also used to enable clocking for CLB2 Reset type: SYSRSn |
0 | EPWM1 | R/W | 0h | EPWM1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] This bit is also used to enable clocking for CLB1 Reset type: SYSRSn |
PCLKCR3 is shown in Figure 3-168 and described in Table 3-185.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ECAP6 | ECAP5 | ECAP4 | ECAP3 | ECAP2 | ECAP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | ECAP6 | R/W | 0h | ECAP6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | ECAP5 | R/W | 0h | ECAP5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | ECAP4 | R/W | 0h | ECAP4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | ECAP3 | R/W | 0h | ECAP3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | ECAP2 | R/W | 0h | ECAP2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | ECAP1 | R/W | 0h | ECAP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR4 is shown in Figure 3-169 and described in Table 3-186.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | EQEP3 | EQEP2 | EQEP1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | EQEP3 | R/W | 0h | EQEP3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | EQEP2 | R/W | 0h | EQEP2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | EQEP1 | R/W | 0h | EQEP1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR6 is shown in Figure 3-170 and described in Table 3-187.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | SD2 | SD1 | |||||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SD2 | R/W | 0h | SD2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | SD1 | R/W | 0h | SD1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR7 is shown in Figure 3-171 and described in Table 3-188.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SCI_D | SCI_C | SCI_B | SCI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | SCI_D | R/W | 0h | SCI_D Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | SCI_C | R/W | 0h | SCI_C Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | SCI_B | R/W | 0h | SCI_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | SCI_A | R/W | 0h | SCI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR8 is shown in Figure 3-172 and described in Table 3-189.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | SPI_C | SPI_B | SPI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | SPI_C | R/W | 0h | SPI_C Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | SPI_B | R/W | 0h | SPI_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | SPI_A | R/W | 0h | SPI_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR9 is shown in Figure 3-173 and described in Table 3-190.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I2C_B | I2C_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | I2C_B | R/W | 0h | I2C_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | I2C_A | R/W | 0h | I2C_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR10 is shown in Figure 3-174 and described in Table 3-191.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | CAN_B | CAN_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | CAN_B | R/W | 0h | CAN_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | CAN_A | R/W | 0h | CAN_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR11 is shown in Figure 3-175 and described in Table 3-192.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | USB_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | McBSP_B | McBSP_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | USB_A | R/W | 0h | USB_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1] This bit is not used (R/W) in CPU2.PCLKCR11 register. USB_A clock enabled is controlled only from CPU1.PCLKCR11 register Reset type: SYSRSn |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | McBSP_B | R/W | 0h | McBSP_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | McBSP_A | R/W | 0h | McBSP_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR12 is shown in Figure 3-176 and described in Table 3-193.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | uPP_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | uPP_A | R/W | 0h | uPP_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Notes: [1]] This bit also affects the uPP message RAM wrapper associated with the respective uPP module [2] This bit is not used (R/W) in CPU2.PCLKCR12 register. UPP_A clock enabled is controlled only from CPU1.PCLKCR12 register Reset type: SYSRSn |
PCLKCR13 is shown in Figure 3-177 and described in Table 3-194.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADC_D | ADC_C | ADC_B | ADC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | ADC_D | R/W | 0h | ADC_D Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | ADC_C | R/W | 0h | ADC_C Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | ADC_B | R/W | 0h | ADC_B Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | ADC_A | R/W | 0h | ADC_A Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR14 is shown in Figure 3-178 and described in Table 3-195.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPSS8 | CMPSS7 | CMPSS6 | CMPSS5 | CMPSS4 | CMPSS3 | CMPSS2 | CMPSS1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-8 | RESERVED | R-0 | 0h | Reserved |
7 | CMPSS8 | R/W | 0h | CMPSS8 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
6 | CMPSS7 | R/W | 0h | CMPSS7 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
5 | CMPSS6 | R/W | 0h | CMPSS6 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
4 | CMPSS5 | R/W | 0h | CMPSS5 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
3 | CMPSS4 | R/W | 0h | CMPSS4 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
2 | CMPSS3 | R/W | 0h | CMPSS3 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
1 | CMPSS2 | R/W | 0h | CMPSS2 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
0 | CMPSS1 | R/W | 0h | CMPSS1 Clock Enable bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
PCLKCR16 is shown in Figure 3-179 and described in Table 3-196.
Return to the Summary Table.
Peripheral Clock Gating Registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | DAC_C | DAC_B | DAC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | DAC_C | R/W | 0h | Buffered_DAC_C Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
17 | DAC_B | R/W | 0h | Buffered_DAC_B Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
16 | DAC_A | R/W | 0h | Buffered_DAC_A Clock Enable Bit: 0: Module clock is gated-off 1: Module clock is turned-on Reset type: SYSRSn |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
SECMSEL is shown in Figure 3-180 and described in Table 3-197.
Return to the Summary Table.
Secondary Master Select register for common peripherals: Selects between CLA & DMA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PF2SEL | PF1SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-14 | RESERVED | R-0 | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | PF2SEL | R/W | 0h | This bit selects whether the dual ported bridge is connected with DMA or CLA as the secondary master (C28x is always connected as primary master) x0: Bridge is connected to CLA x1: Bridge is connected to DMA Reset type: SYSRSn |
1-0 | PF1SEL | R/W | 0h | This bit selects whether the dual ported bridge is connected with DMA or CLA as the secondary master (C28x is always connected as primary master) x0: Bridge is connected to CLA x1: Bridge is connected to DMA Reset type: SYSRSn |
LPMCR is shown in Figure 3-181 and described in Table 3-198.
Return to the Summary Table.
LPM Control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IOISODIS | RESERVED | ||||||
R/W1S-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | M0M1MODE | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WDINTE | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUALSTDBY | LPM | ||||||
R/W-3Fh | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOISODIS | R/W1S | 0h | 0: Indicates IO ISOLATION is not turned ON 1: Indicates IO ISOLATION is turned ON. This bit is set one by hardware ONLY during HIB. This bit cant be set to 1 by software Writing 0 to this bit has not effect. Writing 1 to this bit deactivates IO ISOLATION Notes: [1] This bit is reserved in the register mapped to CPU2 Reset type: raw-XRSn |
30-18 | RESERVED | R-0 | 0h | Reserved |
17-16 | M0M1MODE | R/W | 0h | These bit control the state of CPU1's and CPU2's M0 & M1 memories when Device goes into HIB mode. 00: CPUx's M0 & M1 memories ON with low-leakage mode 01: CPUx's M0 & M1 memories OFF 1x: Reserved Notes: [1] Low-leakage mode for M0 & M1 memories uses the 'Retention' feature of the SRAMs. [2] These bits take effect only when device goes into HIB mode. If the device is not in HIB mode, the value in this bit doesn't control the state of CPU1's and CPU2's M0 & M1 memories Reset type: POR |
15 | WDINTE | R/W | 0h | When this bit is set to 1, it enables the watchdog interrupt signal to wake the device from STANDBY mode. Note: [1] To use this signal, the user must also enable the WDINTn signal using the WDENINT bit in the SCSR register. This signal will not wake the device from HALT mode because the clock to watchdog module is turned off Reset type: SYSRSn |
14-8 | RESERVED | R-0 | 0h | Reserved |
7-2 | QUALSTDBY | R/W | 3Fh | Select number of OSCCLK clock cycles to qualify the selected inputs when waking the from STANDBY mode: 000000 = 2 OSCCLKs 000001 = 3 OSCCLKs ...... 111111 = 65 OSCCLKs Note: The LPMCR.QUALSTDBY register should be set to a value greater than the ratio of INTOSC1/PLLSYSCLK to ensure proper wake up. Reset type: SYSRSn |
1-0 | LPM | R/W | 0h | These bits set the low power mode for the device. Takes effect when CPU executes the IDLE instruction (when IDLE instruction is out of EXE Phase of the Pipeline) 00: IDLE Mode 01: STANDBY Mode 10: HALT Mode (treated as STANDBY for CPU2) 11: HIB Mode (treated as STANDBY for CPU2) Reset type: SYSRSn |
GPIOLPMSEL0 is shown in Figure 3-182 and described in Table 3-199.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO27 | GPIO26 | GPIO25 | GPIO24 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO23 | GPIO22 | GPIO21 | GPIO20 | GPIO19 | GPIO18 | GPIO17 | GPIO16 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO15 | GPIO14 | GPIO13 | GPIO12 | GPIO11 | GPIO10 | GPIO9 | GPIO8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO7 | GPIO6 | GPIO5 | GPIO4 | GPIO3 | GPIO2 | GPIO1 | GPIO0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GPIO31 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
30 | GPIO30 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
29 | GPIO29 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
28 | GPIO28 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
27 | GPIO27 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
26 | GPIO26 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
25 | GPIO25 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
24 | GPIO24 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
23 | GPIO23 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
22 | GPIO22 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
21 | GPIO21 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
20 | GPIO20 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
19 | GPIO19 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
18 | GPIO18 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
17 | GPIO17 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
16 | GPIO16 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
15 | GPIO15 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
14 | GPIO14 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
13 | GPIO13 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
12 | GPIO12 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
11 | GPIO11 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
10 | GPIO10 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
9 | GPIO9 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
8 | GPIO8 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
7 | GPIO7 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
6 | GPIO6 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
5 | GPIO5 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
4 | GPIO4 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
3 | GPIO3 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
2 | GPIO2 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
1 | GPIO1 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
0 | GPIO0 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
GPIOLPMSEL1 is shown in Figure 3-183 and described in Table 3-200.
Return to the Summary Table.
GPIO LPM Wakeup select registers
Connects the selected pin to the LPM circuit. Refer to LPM section of the TRM for the wakeup capabilities of the selected pin.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
GPIO63 | GPIO62 | GPIO61 | GPIO60 | GPIO59 | GPIO58 | GPIO57 | GPIO56 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
GPIO55 | GPIO54 | GPIO53 | GPIO52 | GPIO51 | GPIO50 | GPIO49 | GPIO48 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
GPIO47 | GPIO46 | GPIO45 | GPIO44 | GPIO43 | GPIO42 | GPIO41 | GPIO40 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO39 | GPIO38 | GPIO37 | GPIO36 | GPIO35 | GPIO34 | GPIO33 | GPIO32 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | GPIO63 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
30 | GPIO62 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
29 | GPIO61 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
28 | GPIO60 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
27 | GPIO59 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
26 | GPIO58 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
25 | GPIO57 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
24 | GPIO56 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
23 | GPIO55 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
22 | GPIO54 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
21 | GPIO53 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
20 | GPIO52 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
19 | GPIO51 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
18 | GPIO50 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
17 | GPIO49 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
16 | GPIO48 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
15 | GPIO47 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
14 | GPIO46 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
13 | GPIO45 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
12 | GPIO44 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
11 | GPIO43 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
10 | GPIO42 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
9 | GPIO41 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
8 | GPIO40 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
7 | GPIO39 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
6 | GPIO38 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
5 | GPIO37 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
4 | GPIO36 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
3 | GPIO35 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
2 | GPIO34 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
1 | GPIO33 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
0 | GPIO32 | R/W | 0h | 0 pin is dis-connected from LPM circuit 1 pin is connected to LPM circuit Reset type: SYSRSn |
TMR2CLKCTL is shown in Figure 3-184 and described in Table 3-201.
Return to the Summary Table.
Timer2 Clock Measurement functionality control register
This memory mapped register requires a delay of 69 SYSCLK cycles between subsequent writes to the register, otherwise a second write can be lost. This delay can be realized by adding 69 NOP instructions.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TMR2CLKPRESCALE | TMR2CLKSRCSEL | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-6 | RESERVED | R-0 | 0h | Reserved |
5-3 | TMR2CLKPRESCALE | R/W | 0h | CPU Timer 2 Clock Pre-Scale Value: These bits select the pre-scale value for the selected clock source for CPU Timer 2: 0,0,0,/1 (default on reset) 0,0,1,/2, 0,1,0,/4 0,1,1,/8 1,0,0,/16 1,0,1,spare (defaults to /16) 1,1,0,spare (defaults to /16) 1,1,1,spare (defaults to /16) Note: [1] The CPU Timer2s Clock sync logic detects an input clock edge when configured for any clock source other than SYSCLK and generates an appropriate clock pulse to the CPU timer2. If SYSCLK is approximately the same or less then the input clock source, then the user would need to configure the pre-scale value such that SYSCLK is at least twice as fast as the pre-scaled value. [2] Pre-scaler is bypassed if SYSCLK is selected as the source of CPU Timer 2 in TMR2CLKSRCSEL of TMR2CLKCTL. Reset type: SYSRSn |
2-0 | TMR2CLKSRCSEL | R/W | 0h | CPU Timer 2 Clock Source Select Bit: This bit selects the source for CPU Timer 2: 000 =SYSCLK Selected (default on reset, pre-scale is bypassed) 001 = INTOSC1 010 = INTOSC2 011 = XTAL 100 = Reserved 101 = Reserved 110 = AUXPLLCLK 111 = reserved Reset type: SYSRSn |
RESC is shown in Figure 3-185 and described in Table 3-202.
Return to the Summary Table.
Reset Cause register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TRSTn_pin_status | XRSn_pin_status | RESERVED | |||||
R-0h | R-0h | R-0-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SCCRESETn | ||||||
R-0-0h | R/W1C-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HIBRESETn | HWBISTn | RESERVED | NMIWDRSn | WDRSn | XRSn | POR |
R-0-0h | R/W1C-0h | R/W1C-0h | R-0-0h | R/W1C-0h | R/W1C-0h | R/W1C-1h | R/W1C-1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | TRSTn_pin_status | R | 0h | Reading this bit provides the current status of TRSTn at the respective C28x CPUs TRSTn input port. Reset value is reflective of the pin status. Reset type: N/A |
30 | XRSn_pin_status | R | 0h | Reading this bit provides the current status of the XRSn pin. Reset value is reflective of the pin status. Reset type: N/A |
29-16 | RESERVED | R-0 | 0h | Reserved |
15-9 | RESERVED | R-0 | 0h | Reserved |
8 | SCCRESETn | R/W1C | 0h | If this bit is set, indicates that the device was reset by SCCRESETn (fired by DCSM). Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
7 | RESERVED | R-0 | 0h | Reserved |
6 | HIBRESETn | R/W1C | 0h | If this bit is set, indicates that the device was reset due to a Hibernate mode Wakeup. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: raw-XRSn |
5 | HWBISTn | R/W1C | 0h | If this bit is set, indicates that the device was reset by HWBIST. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
4 | RESERVED | R-0 | 0h | Reserved |
3 | NMIWDRSn | R/W1C | 0h | If this bit is set, indicates that the device was reset by NMIWDRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. To know the exact cause of NMI after the reset, software needs to read CPU1/2.NMISHDFLG registers Reset type: POR |
2 | WDRSn | R/W1C | 0h | If this bit is set, indicates that the device was reset by WDRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
1 | XRSn | R/W1C | 1h | If this bit is set, indicates that the device was reset by XRSn. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |
0 | POR | R/W1C | 1h | If this bit is set, indicates that the device was reset by PORn. This bit is cleared by the Boot-ROM. As such, this bit cannot be used by the application to determine a POR. Writing a 1 to this bit will force the bit to 0 Writing of 0 will have no effect. Reset type: POR |