SPRUHM8K December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
Table 3-241 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-241 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DxLOCK | Dedicated RAM Config Lock Register | EALLOW | Go |
2h | DxCOMMIT | Dedicated RAM Config Lock Commit Register | EALLOW | Go |
8h | DxACCPROT0 | Dedicated RAM Config Register | EALLOW | Go |
10h | DxTEST | Dedicated RAM TEST Register | EALLOW | Go |
12h | DxINIT | Dedicated RAM Init Register | EALLOW | Go |
14h | DxINITDONE | Dedicated RAM InitDone Status Register | Go | |
20h | LSxLOCK | Local Shared RAM Config Lock Register | EALLOW | Go |
22h | LSxCOMMIT | Local Shared RAM Config Lock Commit Register | EALLOW | Go |
24h | LSxMSEL | Local Shared RAM Master Sel Register | EALLOW | Go |
26h | LSxCLAPGM | Local Shared RAM Prog/Exe control Register | EALLOW | Go |
28h | LSxACCPROT0 | Local Shared RAM Config Register 0 | EALLOW | Go |
2Ah | LSxACCPROT1 | Local Shared RAM Config Register 1 | EALLOW | Go |
30h | LSxTEST | Local Shared RAM TEST Register | EALLOW | Go |
32h | LSxINIT | Local Shared RAM Init Register | EALLOW | Go |
34h | LSxINITDONE | Local Shared RAM InitDone Status Register | Go | |
40h | GSxLOCK | Global Shared RAM Config Lock Register | EALLOW | Go |
42h | GSxCOMMIT | Global Shared RAM Config Lock Commit Register | EALLOW | Go |
44h | GSxMSEL | Global Shared RAM Master Sel Register | EALLOW | Go |
48h | GSxACCPROT0 | Global Shared RAM Config Register 0 | EALLOW | Go |
4Ah | GSxACCPROT1 | Global Shared RAM Config Register 1 | EALLOW | Go |
4Ch | GSxACCPROT2 | Global Shared RAM Config Register 2 | EALLOW | Go |
4Eh | GSxACCPROT3 | Global Shared RAM Config Register 3 | EALLOW | Go |
50h | GSxTEST | Global Shared RAM TEST Register | EALLOW | Go |
52h | GSxINIT | Global Shared RAM Init Register | EALLOW | Go |
54h | GSxINITDONE | Global Shared RAM InitDone Status Register | Go | |
70h | MSGxTEST | Message RAM TEST Register | EALLOW | Go |
72h | MSGxINIT | Message RAM Init Register | EALLOW | Go |
74h | MSGxINITDONE | Message RAM InitDone Status Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-242 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DxLOCK is shown in Figure 3-216 and described in Table 3-243.
Return to the Summary Table.
Dedicated RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_D1 | LOCK_D0 | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | LOCK_D1 | R/W | 0h | Locks the write to access protection and master select fields for D1 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_D0 | R/W | 0h | Locks the write to access protection and master select fields for D0 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
1-0 | RESERVED | R | 0h | Reserved |
DxCOMMIT is shown in Figure 3-217 and described in Table 3-244.
Return to the Summary Table.
Dedicated RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_D1 | COMMIT_D0 | RESERVED | ||||
R-0h | R/WSonce-0h | R/WSonce-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | COMMIT_D1 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for D1 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_D0 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for D0 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
1-0 | RESERVED | R | 0h | Reserved |
DxACCPROT0 is shown in Figure 3-218 and described in Table 3-245.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_D1 | FETCHPROT_D1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_D0 | FETCHPROT_D0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_D1 | R/W | 0h | CPU WR Protection For D1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_D1 | R/W | 0h | Fetch Protection For D1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_D0 | R/W | 0h | CPU WR Protection For D0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
16 | FETCHPROT_D0 | R/W | 0h | Fetch Protection For D0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-0 | RESERVED | R | 0h | Reserved |
DxTEST is shown in Figure 3-219 and described in Table 3-246.
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Dedicated RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_D1 | TEST_D0 | TEST_M1 | TEST_M0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7-6 | TEST_D1 | R/W | 0h | Selects the different modes for D1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
5-4 | TEST_D0 | R/W | 0h | Selects the different modes for D0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
3-2 | TEST_M1 | R/W | 0h | Selects the different modes for M1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_M0 | R/W | 0h | Selects the different modes for M0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
DxINIT is shown in Figure 3-220 and described in Table 3-247.
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Dedicated RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_D1 | INIT_D0 | INIT_M1 | INIT_M0 | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INIT_D1 | R-0/W1S | 0h | RAM Initialization control for D1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_D0 | R-0/W1S | 0h | RAM Initialization control for D0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_M1 | R-0/W1S | 0h | RAM Initialization control for M1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_M0 | R-0/W1S | 0h | RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
DxINITDONE is shown in Figure 3-221 and described in Table 3-248.
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Dedicated RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_D1 | INITDONE_D0 | INITDONE_M1 | INITDONE_M0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | INITDONE_D1 | R | 0h | RAM Initialization status for D1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_D0 | R | 0h | RAM Initialization status for D0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_M1 | R | 0h | RAM Initialization status for M1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_M0 | R | 0h | RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
LSxLOCK is shown in Figure 3-222 and described in Table 3-249.
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Local Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LOCK_LS5 | LOCK_LS4 | LOCK_LS3 | LOCK_LS2 | LOCK_LS1 | LOCK_LS0 | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5 | LOCK_LS5 | R/W | 0h | Locks the write to access protection and master select fields for LS5 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
4 | LOCK_LS4 | R/W | 0h | Locks the write to access protection and master select fields for LS4 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
3 | LOCK_LS3 | R/W | 0h | Locks the write to access protection and master select fields for LS3 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_LS2 | R/W | 0h | Locks the write to access protection and master select fields for LS2 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
1 | LOCK_LS1 | R/W | 0h | Locks the write to access protection and master select fields for LS1 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_LS0 | R/W | 0h | Locks the write to access protection and master select fields for LS0 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
LSxCOMMIT is shown in Figure 3-223 and described in Table 3-250.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COMMIT_LS5 | COMMIT_LS4 | COMMIT_LS3 | COMMIT_LS2 | COMMIT_LS1 | COMMIT_LS0 | |
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5 | COMMIT_LS5 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS5 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_LS4 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS4 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
3 | COMMIT_LS3 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS3 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_LS2 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS2 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_LS1 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS1 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_LS0 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for LS0 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
LSxMSEL is shown in Figure 3-224 and described in Table 3-251.
Return to the Summary Table.
Local Shared RAM Master Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MSEL_LS5 | MSEL_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSEL_LS3 | MSEL_LS2 | MSEL_LS1 | MSEL_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R | 0h | Reserved |
11-10 | MSEL_LS5 | R/W | 0h | Master Select for LS5 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
9-8 | MSEL_LS4 | R/W | 0h | Master Select for LS4 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
7-6 | MSEL_LS3 | R/W | 0h | Master Select for LS3 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
5-4 | MSEL_LS2 | R/W | 0h | Master Select for LS2 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
3-2 | MSEL_LS1 | R/W | 0h | Master Select for LS1 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
1-0 | MSEL_LS0 | R/W | 0h | Master Select for LS0 RAM: 00: Memory is dedicated to CPU. 01: Memory is shared between CPU and CLA1. 10: Reserved. 11: Reserved. Reset type: SYSRSn |
LSxCLAPGM is shown in Figure 3-225 and described in Table 3-252.
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Local Shared RAM Prog/Exe control Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLAPGM_LS5 | CLAPGM_LS4 | CLAPGM_LS3 | CLAPGM_LS2 | CLAPGM_LS1 | CLAPGM_LS0 | |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5 | CLAPGM_LS5 | R/W | 0h | Selects LS5 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
4 | CLAPGM_LS4 | R/W | 0h | Selects LS4 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
3 | CLAPGM_LS3 | R/W | 0h | Selects LS3 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
2 | CLAPGM_LS2 | R/W | 0h | Selects LS2 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
1 | CLAPGM_LS1 | R/W | 0h | Selects LS1 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
0 | CLAPGM_LS0 | R/W | 0h | Selects LS0 RAM as program vs data memory for CLA: 0: CLA Data memory. 1: CLA Program memory. Reset type: SYSRSn |
LSxACCPROT0 is shown in Figure 3-226 and described in Table 3-253.
Return to the Summary Table.
Local Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS3 | FETCHPROT_LS3 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS2 | FETCHPROT_LS2 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS1 | FETCHPROT_LS1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS0 | FETCHPROT_LS0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS3 | R/W | 0h | CPU WR Protection For LS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS3 | R/W | 0h | Fetch Protection For LS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS2 | R/W | 0h | CPU WR Protection For LS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS2 | R/W | 0h | Fetch Protection For LS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS1 | R/W | 0h | CPU WR Protection For LS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS1 | R/W | 0h | Fetch Protection For LS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS0 | R/W | 0h | CPU WR Protection For LS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS0 | R/W | 0h | Fetch Protection For LS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxACCPROT1 is shown in Figure 3-227 and described in Table 3-254.
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Local Shared RAM Config Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS5 | FETCHPROT_LS5 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS4 | FETCHPROT_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS5 | R/W | 0h | CPU WR Protection For LS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS5 | R/W | 0h | Fetch Protection For LS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS4 | R/W | 0h | CPU WR Protection For LS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS4 | R/W | 0h | Fetch Protection For LS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxTEST is shown in Figure 3-228 and described in Table 3-255.
Return to the Summary Table.
Local Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TEST_LS5 | TEST_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_LS3 | TEST_LS2 | TEST_LS1 | TEST_LS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R | 0h | Reserved |
11-10 | TEST_LS5 | R/W | 0h | Selects the different modes for LS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
9-8 | TEST_LS4 | R/W | 0h | Selects the different modes for LS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
7-6 | TEST_LS3 | R/W | 0h | Selects the different modes for LS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
5-4 | TEST_LS2 | R/W | 0h | Selects the different modes for LS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
3-2 | TEST_LS1 | R/W | 0h | Selects the different modes for LS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_LS0 | R/W | 0h | Selects the different modes for LS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
LSxINIT is shown in Figure 3-229 and described in Table 3-256.
Return to the Summary Table.
Local Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_LS5 | INIT_LS4 | INIT_LS3 | INIT_LS2 | INIT_LS1 | INIT_LS0 | |
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5 | INIT_LS5 | R-0/W1S | 0h | RAM Initialization control for LS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_LS4 | R-0/W1S | 0h | RAM Initialization control for LS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | INIT_LS3 | R-0/W1S | 0h | RAM Initialization control for LS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_LS2 | R-0/W1S | 0h | RAM Initialization control for LS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_LS1 | R-0/W1S | 0h | RAM Initialization control for LS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_LS0 | R-0/W1S | 0h | RAM Initialization control for LS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
LSxINITDONE is shown in Figure 3-230 and described in Table 3-257.
Return to the Summary Table.
Local Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INITDONE_LS5 | INITDONE_LS4 | INITDONE_LS3 | INITDONE_LS2 | INITDONE_LS1 | INITDONE_LS0 | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-6 | RESERVED | R | 0h | Reserved |
5 | INITDONE_LS5 | R | 0h | RAM Initialization status for LS5 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | INITDONE_LS4 | R | 0h | RAM Initialization status for LS4 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
3 | INITDONE_LS3 | R | 0h | RAM Initialization status for LS3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_LS2 | R | 0h | RAM Initialization status for LS2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_LS1 | R | 0h | RAM Initialization status for LS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_LS0 | R | 0h | RAM Initialization status for LS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
GSxLOCK is shown in Figure 3-231 and described in Table 3-258.
Return to the Summary Table.
Global Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK_GS15 | LOCK_GS14 | LOCK_GS13 | LOCK_GS12 | LOCK_GS11 | LOCK_GS10 | LOCK_GS9 | LOCK_GS8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_GS7 | LOCK_GS6 | LOCK_GS5 | LOCK_GS4 | LOCK_GS3 | LOCK_GS2 | LOCK_GS1 | LOCK_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | LOCK_GS15 | R/W | 0h | Locks the write to access protection and master select fields for GS15 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
14 | LOCK_GS14 | R/W | 0h | Locks the write to access protection and master select fields for GS14 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
13 | LOCK_GS13 | R/W | 0h | Locks the write to access protection and master select fields for GS13 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
12 | LOCK_GS12 | R/W | 0h | Locks the write to access protection and master select fields for GS12 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
11 | LOCK_GS11 | R/W | 0h | Locks the write to access protection and master select fields for GS11 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
10 | LOCK_GS10 | R/W | 0h | Locks the write to access protection and master select fields for GS10 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
9 | LOCK_GS9 | R/W | 0h | Locks the write to access protection and master select fields for GS9 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
8 | LOCK_GS8 | R/W | 0h | Locks the write to access protection and master select fields for GS8 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
7 | LOCK_GS7 | R/W | 0h | Locks the write to access protection and master select fields for GS7 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
6 | LOCK_GS6 | R/W | 0h | Locks the write to access protection and master select fields for GS6 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
5 | LOCK_GS5 | R/W | 0h | Locks the write to access protection and master select fields for GS5 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
4 | LOCK_GS4 | R/W | 0h | Locks the write to access protection and master select fields for GS4 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
3 | LOCK_GS3 | R/W | 0h | Locks the write to access protection and master select fields for GS3 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
2 | LOCK_GS2 | R/W | 0h | Locks the write to access protection and master select fields for GS2 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
1 | LOCK_GS1 | R/W | 0h | Locks the write to access protection and master select fields for GS1 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_GS0 | R/W | 0h | Locks the write to access protection and master select fields for GS0 RAM: 0: Write to ACCPROT and Mselect fields are allowed. 1: Write to ACCPROT and Mselect fields are blocked. Reset type: SYSRSn |
GSxCOMMIT is shown in Figure 3-232 and described in Table 3-259.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COMMIT_GS15 | COMMIT_GS14 | COMMIT_GS13 | COMMIT_GS12 | COMMIT_GS11 | COMMIT_GS10 | COMMIT_GS9 | COMMIT_GS8 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_GS7 | COMMIT_GS6 | COMMIT_GS5 | COMMIT_GS4 | COMMIT_GS3 | COMMIT_GS2 | COMMIT_GS1 | COMMIT_GS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | COMMIT_GS15 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS15 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
14 | COMMIT_GS14 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS14 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
13 | COMMIT_GS13 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS13 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
12 | COMMIT_GS12 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS12 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
11 | COMMIT_GS11 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS11 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
10 | COMMIT_GS10 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS10 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
9 | COMMIT_GS9 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS9 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
8 | COMMIT_GS8 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS2 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
7 | COMMIT_GS7 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS7 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
6 | COMMIT_GS6 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS6 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_GS5 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS5 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_GS4 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS4 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
3 | COMMIT_GS3 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS3 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
2 | COMMIT_GS2 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS2 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
1 | COMMIT_GS1 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS1 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_GS0 | R/WSonce | 0h | Permanently Locks the write to access protection and master select fields for GS0 RAM: 0: Write to ACCPROT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT and Mselect fields are permanently blocked. Reset type: SYSRSn |
GSxMSEL is shown in Figure 3-233 and described in Table 3-260.
Return to the Summary Table.
Global Shared RAM Master Sel Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MSEL_GS15 | MSEL_GS14 | MSEL_GS13 | MSEL_GS12 | MSEL_GS11 | MSEL_GS10 | MSEL_GS9 | MSEL_GS8 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSEL_GS7 | MSEL_GS6 | MSEL_GS5 | MSEL_GS4 | MSEL_GS3 | MSEL_GS2 | MSEL_GS1 | MSEL_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | MSEL_GS15 | R/W | 0h | Master Select for GS15 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
14 | MSEL_GS14 | R/W | 0h | Master Select for GS14 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
13 | MSEL_GS13 | R/W | 0h | Master Select for GS13 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
12 | MSEL_GS12 | R/W | 0h | Master Select for GS12 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
11 | MSEL_GS11 | R/W | 0h | Master Select for GS11 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
10 | MSEL_GS10 | R/W | 0h | Master Select for GS10 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
9 | MSEL_GS9 | R/W | 0h | Master Select for GS9 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
8 | MSEL_GS8 | R/W | 0h | Master Select for GS8 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
7 | MSEL_GS7 | R/W | 0h | Master Select for GS7 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
6 | MSEL_GS6 | R/W | 0h | Master Select for GS6 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
5 | MSEL_GS5 | R/W | 0h | Master Select for GS5 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
4 | MSEL_GS4 | R/W | 0h | Master Select for GS4 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
3 | MSEL_GS3 | R/W | 0h | Master Select for GS3 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
2 | MSEL_GS2 | R/W | 0h | Master Select for GS2 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
1 | MSEL_GS1 | R/W | 0h | Master Select for GS1 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
0 | MSEL_GS0 | R/W | 0h | Master Select for GS0 RAM: 0: CPU1 is master for this memory. 1: CPU2 is master for this memory. Reset type: CPU1.SYSRSn |
GSxACCPROT0 is shown in Figure 3-234 and described in Table 3-261.
Return to the Summary Table.
Global Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS3 | CPUWRPROT_GS3 | FETCHPROT_GS3 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS2 | CPUWRPROT_GS2 | FETCHPROT_GS2 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS1 | CPUWRPROT_GS1 | FETCHPROT_GS1 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS0 | CPUWRPROT_GS0 | FETCHPROT_GS0 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS3 | R/W | 0h | DMA WR Protection For GS3 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS3 | R/W | 0h | CPU WR Protection For GS3 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS3 | R/W | 0h | Fetch Protection For GS3 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS2 | R/W | 0h | DMA WR Protection For GS2 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS2 | R/W | 0h | CPU WR Protection For GS2 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS2 | R/W | 0h | Fetch Protection For GS2 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS1 | R/W | 0h | DMA WR Protection For GS1 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS1 | R/W | 0h | CPU WR Protection For GS1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS1 | R/W | 0h | Fetch Protection For GS1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS0 | R/W | 0h | DMA WR Protection For GS0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS0 | R/W | 0h | CPU WR Protection For GS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS0 | R/W | 0h | Fetch Protection For GS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT1 is shown in Figure 3-235 and described in Table 3-262.
Return to the Summary Table.
Global Shared RAM Config Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS7 | CPUWRPROT_GS7 | FETCHPROT_GS7 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS6 | CPUWRPROT_GS6 | FETCHPROT_GS6 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS5 | CPUWRPROT_GS5 | FETCHPROT_GS5 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS4 | CPUWRPROT_GS4 | FETCHPROT_GS4 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS7 | R/W | 0h | DMA WR Protection For GS7 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS7 | R/W | 0h | CPU WR Protection For GS7 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS7 | R/W | 0h | Fetch Protection For GS7 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS6 | R/W | 0h | DMA WR Protection For GS6 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS6 | R/W | 0h | CPU WR Protection For GS6 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS6 | R/W | 0h | Fetch Protection For GS6 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS5 | R/W | 0h | DMA WR Protection For GS5 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS5 | R/W | 0h | CPU WR Protection For GS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS5 | R/W | 0h | Fetch Protection For GS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS4 | R/W | 0h | DMA WR Protection For GS4 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS4 | R/W | 0h | CPU WR Protection For GS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS4 | R/W | 0h | Fetch Protection For GS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT2 is shown in Figure 3-236 and described in Table 3-263.
Return to the Summary Table.
Global Shared RAM Config Register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS11 | CPUWRPROT_GS11 | FETCHPROT_GS11 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS10 | CPUWRPROT_GS10 | FETCHPROT_GS10 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS9 | CPUWRPROT_GS9 | FETCHPROT_GS9 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS8 | CPUWRPROT_GS8 | FETCHPROT_GS8 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS11 | R/W | 0h | DMA WR Protection For GS11 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS11 | R/W | 0h | CPU WR Protection For GS11 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS11 | R/W | 0h | Fetch Protection For GS11 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS10 | R/W | 0h | DMA WR Protection For GS10 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS10 | R/W | 0h | CPU WR Protection For GS10 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS10 | R/W | 0h | Fetch Protection For GS10 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS9 | R/W | 0h | DMA WR Protection For GS9 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS9 | R/W | 0h | CPU WR Protection For GS9 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS9 | R/W | 0h | Fetch Protection For GS9 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS8 | R/W | 0h | DMA WR Protection For GS8 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS8 | R/W | 0h | CPU WR Protection For GS8 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS8 | R/W | 0h | Fetch Protection For GS8 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxACCPROT3 is shown in Figure 3-237 and described in Table 3-264.
Return to the Summary Table.
Global Shared RAM Config Register 3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | DMAWRPROT_GS15 | CPUWRPROT_GS15 | FETCHPROT_GS15 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | DMAWRPROT_GS14 | CPUWRPROT_GS14 | FETCHPROT_GS14 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAWRPROT_GS13 | CPUWRPROT_GS13 | FETCHPROT_GS13 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMAWRPROT_GS12 | CPUWRPROT_GS12 | FETCHPROT_GS12 | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | DMAWRPROT_GS15 | R/W | 0h | DMA WR Protection For GS15 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
25 | CPUWRPROT_GS15 | R/W | 0h | CPU WR Protection For GS15 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_GS15 | R/W | 0h | Fetch Protection For GS15 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-19 | RESERVED | R | 0h | Reserved |
18 | DMAWRPROT_GS14 | R/W | 0h | DMA WR Protection For GS14 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
17 | CPUWRPROT_GS14 | R/W | 0h | CPU WR Protection For GS14 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_GS14 | R/W | 0h | Fetch Protection For GS14 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-11 | RESERVED | R | 0h | Reserved |
10 | DMAWRPROT_GS13 | R/W | 0h | DMA WR Protection For GS13 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
9 | CPUWRPROT_GS13 | R/W | 0h | CPU WR Protection For GS13 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_GS13 | R/W | 0h | Fetch Protection For GS13 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-3 | RESERVED | R | 0h | Reserved |
2 | DMAWRPROT_GS12 | R/W | 0h | DMA WR Protection For GS12 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS12 | R/W | 0h | CPU WR Protection For GS12 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS12 | R/W | 0h | Fetch Protection For GS12 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxTEST is shown in Figure 3-238 and described in Table 3-265.
Return to the Summary Table.
Global Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TEST_GS15 | TEST_GS14 | TEST_GS13 | TEST_GS12 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TEST_GS11 | TEST_GS10 | TEST_GS9 | TEST_GS8 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_GS7 | TEST_GS6 | TEST_GS5 | TEST_GS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_GS3 | TEST_GS2 | TEST_GS1 | TEST_GS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | TEST_GS15 | R/W | 0h | Selects the different modes for GS15 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
29-28 | TEST_GS14 | R/W | 0h | Selects the different modes for GS14 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
27-26 | TEST_GS13 | R/W | 0h | Selects the different modes for GS13 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
25-24 | TEST_GS12 | R/W | 0h | Selects the different modes for GS12 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
23-22 | TEST_GS11 | R/W | 0h | Selects the different modes for GS11 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
21-20 | TEST_GS10 | R/W | 0h | Selects the different modes for GS10 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
19-18 | TEST_GS9 | R/W | 0h | Selects the different modes for GS9 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
17-16 | TEST_GS8 | R/W | 0h | Selects the different modes for GS8 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
15-14 | TEST_GS7 | R/W | 0h | Selects the different modes for GS7 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
13-12 | TEST_GS6 | R/W | 0h | Selects the different modes for GS6 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
11-10 | TEST_GS5 | R/W | 0h | Selects the different modes for GS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
9-8 | TEST_GS4 | R/W | 0h | Selects the different modes for GS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
7-6 | TEST_GS3 | R/W | 0h | Selects the different modes for GS3 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
5-4 | TEST_GS2 | R/W | 0h | Selects the different modes for GS2 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
3-2 | TEST_GS1 | R/W | 0h | Selects the different modes for GS1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_GS0 | R/W | 0h | Selects the different modes for GS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
GSxINIT is shown in Figure 3-239 and described in Table 3-266.
Return to the Summary Table.
Global Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INIT_GS15 | INIT_GS14 | INIT_GS13 | INIT_GS12 | INIT_GS11 | INIT_GS10 | INIT_GS9 | INIT_GS8 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_GS7 | INIT_GS6 | INIT_GS5 | INIT_GS4 | INIT_GS3 | INIT_GS2 | INIT_GS1 | INIT_GS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | INIT_GS15 | R-0/W1S | 0h | RAM Initialization control for GS15 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
14 | INIT_GS14 | R-0/W1S | 0h | RAM Initialization control for GS14 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
13 | INIT_GS13 | R-0/W1S | 0h | RAM Initialization control for GS13 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
12 | INIT_GS12 | R-0/W1S | 0h | RAM Initialization control for GS12 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
11 | INIT_GS11 | R-0/W1S | 0h | RAM Initialization control for GS11 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
10 | INIT_GS10 | R-0/W1S | 0h | RAM Initialization control for GS10 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
9 | INIT_GS9 | R-0/W1S | 0h | RAM Initialization control for GS9 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
8 | INIT_GS8 | R-0/W1S | 0h | RAM Initialization control for GS8 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
7 | INIT_GS7 | R-0/W1S | 0h | RAM Initialization control for GS7 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_GS6 | R-0/W1S | 0h | RAM Initialization control for GS6 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_GS5 | R-0/W1S | 0h | RAM Initialization control for GS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_GS4 | R-0/W1S | 0h | RAM Initialization control for GS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | INIT_GS3 | R-0/W1S | 0h | RAM Initialization control for GS3 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
2 | INIT_GS2 | R-0/W1S | 0h | RAM Initialization control for GS2 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_GS1 | R-0/W1S | 0h | RAM Initialization control for GS1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_GS0 | R-0/W1S | 0h | RAM Initialization control for GS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
GSxINITDONE is shown in Figure 3-240 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
INITDONE_GS15 | INITDONE_GS14 | INITDONE_GS13 | INITDONE_GS12 | INITDONE_GS11 | INITDONE_GS10 | INITDONE_GS9 | INITDONE_GS8 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITDONE_GS7 | INITDONE_GS6 | INITDONE_GS5 | INITDONE_GS4 | INITDONE_GS3 | INITDONE_GS2 | INITDONE_GS1 | INITDONE_GS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | INITDONE_GS15 | R | 0h | RAM Initialization status for GS15 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
14 | INITDONE_GS14 | R | 0h | RAM Initialization status for GS14 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
13 | INITDONE_GS13 | R | 0h | RAM Initialization status for GS13 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
12 | INITDONE_GS12 | R | 0h | RAM Initialization status for GS12 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
11 | INITDONE_GS11 | R | 0h | RAM Initialization status for GS11 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
10 | INITDONE_GS10 | R | 0h | RAM Initialization status for GS10 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
9 | INITDONE_GS9 | R | 0h | RAM Initialization status for GS9 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
8 | INITDONE_GS8 | R | 0h | RAM Initialization status for GS8 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
7 | INITDONE_GS7 | R | 0h | RAM Initialization status for GS7 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
6 | INITDONE_GS6 | R | 0h | RAM Initialization status for GS6 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_GS5 | R | 0h | RAM Initialization status for GS5 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | INITDONE_GS4 | R | 0h | RAM Initialization status for GS4 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
3 | INITDONE_GS3 | R | 0h | RAM Initialization status for GS3 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
2 | INITDONE_GS2 | R | 0h | RAM Initialization status for GS2 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_GS1 | R | 0h | RAM Initialization status for GS1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_GS0 | R | 0h | RAM Initialization status for GS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
MSGxTEST is shown in Figure 3-241 and described in Table 3-268.
Return to the Summary Table.
Message RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TEST_CLA1TOCPU | TEST_CPUTOCLA1 | TEST_CPUTOCPU | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | TEST_CLA1TOCPU | R/W | 0h | Selects the different modes for CLA1TOCPU MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
3-2 | TEST_CPUTOCLA1 | R/W | 0h | Selects the different modes for CPUTOCLA1 MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_CPUTOCPU | R/W | 0h | Selects the different modes for CPUTOCPU MSG RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
MSGxINIT is shown in Figure 3-242 and described in Table 3-269.
Return to the Summary Table.
Message RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | INIT_CLA1TOCPU | INIT_CPUTOCLA1 | INIT_CPUTOCPU | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | INIT_CLA1TOCPU | R-0/W1S | 0h | RAM Initialization control for CLA1TOCPU MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
1 | INIT_CPUTOCLA1 | R-0/W1S | 0h | RAM Initialization control for CPUTOCLA1 MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_CPUTOCPU | R-0/W1S | 0h | RAM Initialization control for CPUTOCPU MSG RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
MSGxINITDONE is shown in Figure 3-243 and described in Table 3-270.
Return to the Summary Table.
Message RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | INITDONE_CLA1TOCPU | INITDONE_CPUTOCLA1 | INITDONE_CPUTOCPU | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | INITDONE_CLA1TOCPU | R | 0h | RAM Initialization status for CLA1TOCPU MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
1 | INITDONE_CPUTOCLA1 | R | 0h | RAM Initialization status for CPUTOCLA1 MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
0 | INITDONE_CPUTOCPU | R | 0h | RAM Initialization status for CPUTOCPU MSG RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |