The fields of the SDRAM timing register (SDRAM_TR)
must be programmed first as described in Table 25-27 to satisfy the required timing parameters for the K4S641632H-TC(L)70. Based on
these calculations, a value of 6111 4610h must be written to the SDRAM_TR. Figure 25-16 shows a graphical description of how the SDRAM_TR must be programmed.
Table 25-27 SDRAM_TR Field Calculations for EMIF to K4S641632H-TC(L)70 InterfaceField Name | Formula | Value from K4S641632H-TC(L)70 Data
Sheet | Value Calculated for Field |
---|
T_RFC | T_RFC >= (tRFC × fEM1CLK) - 1 | tRC = 68 ns (min)(1) | 6 |
T_RP | T_RP >= (tRP × fEM1CLK) - 1 | tRP = 20 ns (min) | 1 |
T_RCD | T_RCD >= (tRCD × fEM1CLK) - 1 | tRCD = 20 ns (min) | 1 |
T_WR | T_WR >= (tWR × fEM1CLK) - 1 | tRDL = 2 CLK = 20 ns (min)(2) | 1 |
T_RAS | T_RAS >= (tRAS × fEM1CLK) - 1 | tRAS = 49 ns (min) | 4 |
T_RC | T_RC >= (tRC × fEM1CLK) - 1 | tRC = 68 ns (min) | 6 |
T_RRD | T_RRD >= (tRRD × fEM1CLK) - 1 | tRRD = 14 ns (min) | 1 |
(1) The Samsung data sheet does not specify a tRFC value. Instead,
Samsung specifies tRC as the minimum auto refresh period.
(2) The Samsung data sheet does not specify a tWR value. Instead,
Samsung specifies tRDL as last data in to row precharge minimum
delay.
Figure 25-16 SDRAM Timing Register (SDRAM_TR)31 | 30 | 29 | 28 | 27 | 26 | | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
T_RFC | T_RP | Rsvd | T_RCD | Rsvd | T_WR |
T_RAS | T_RC | Rsvd | T_RRD | Reserved |