The USB test mode 8-bit register (USBTEST) is primarily used to put the USB controller into one of the four test modes for operation described in the USB Specification 2.0 , in response to a SET FEATURE: USBTESTMODE command. This register is not used in normal operation.
Note: Only one of these bits should be set at any time.
USBTEST in Host Mode is shown in Figure 23-16 and described in Table 23-18.
Figure 23-16 USB Test Mode Register (USBTEST) in Host Mode FORCEH | FIFOACC | FORCEFS | Reserved |
LEGEND: R/W = Read/Write; R = Read only; -n =
value after reset |
Table 23-18 USB Test Mode Register (USBTEST) in Host Mode Field DescriptionsBit | Field | Value | Description |
---|
7 | FORCEH | | Force Host Mode. While in this mode, status of the bus connection may be read using the DEV bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit. |
0 | No effect |
1 | Forces the USB controller to enter Host mode when the SESSION bit is set, regardless of whether the USB controller is connected to any peripheral. The state of the USB0DP and USB0DM signals is ignored. The USB controller then remains in Host mode until the SESSION bit is cleared, even if a Device is disconnected. If the FORCEH bit remains set, the USB controller re-enters Host mode the next time the SESSION bit is set. |
6 | FIFOACC | | FIFO Access |
0 | No effect |
1 | Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. |
5 | FORCEFS | | Force Full-Speed Mode |
0 | The USB controller operates at Low Speed. |
1 | Forces the USB controller into Full-Speed mode upon receiving a USB RESET. |
4-0 | Reserved | 0 | Reserved |
USBTEST in Device Mode is
shown in Figure 23-17 and described in Table 23-19.
Figure 23-17 USB Test Mode Register (USBTEST) in Device Mode Reserved | FIFOACC | FORCEFS | Reserved |
LEGEND: R/W = Read/Write; R = Read only; -n =
value after reset |
Table 23-19 USB Test Mode Register (USBTEST) in Device Mode Field DescriptionsBit | Field | Value | Description |
---|
7 | Reserved | | Force Host Mode. While in this mode, status of the bus connection may be read using the DEV bit of the USBDEVCTL register. The operating speed is determined from the FORCEFS bit. |
6 | FIFOACC | | FIFO Access |
0 | No effect |
1 | Transfers the packet in the endpoint 0 transmit FIFO to the endpoint 0 receive FIFO. |
5 | FORCEFS | | Force Full-Speed Mode |
0 | The USB controller operates at Low Speed. |
1 | Forces the USB controller into Full-Speed mode upon receiving a USB RESET. |
4-0 | Reserved | 0 | Reserved |