SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 24-15 lists the memory-mapped registers for the CLB_LOGIC_CONFIG_REGS registers. All register offset addresses not listed in Table 24-15 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
2h | CLB_COUNT_RESET | Counter Block RESET | EALLOW, LOCK | Go |
4h | CLB_COUNT_MODE_1 | Counter Block MODE_1 | EALLOW, LOCK | Go |
6h | CLB_COUNT_MODE_0 | Counter Block MODE_0 | EALLOW, LOCK | Go |
8h | CLB_COUNT_EVENT | Counter Block EVENT | EALLOW, LOCK | Go |
Ah | CLB_FSM_EXTRA_IN0 | FSM Extra EXT_IN0 | EALLOW, LOCK | Go |
Ch | CLB_FSM_EXTERNAL_IN0 | FSM EXT_IN0 | EALLOW, LOCK | Go |
Eh | CLB_FSM_EXTERNAL_IN1 | FSM_EXT_IN1 | EALLOW, LOCK | Go |
10h | CLB_FSM_EXTRA_IN1 | FSM Extra_EXT_IN1 | EALLOW, LOCK | Go |
12h | CLB_LUT4_IN0 | LUT4_0/1/2 IN0 input source | EALLOW, LOCK | Go |
14h | CLB_LUT4_IN1 | LUT4_0/1/2 IN1 input source | EALLOW, LOCK | Go |
16h | CLB_LUT4_IN2 | LUT4_0/1/2 IN2 input source | EALLOW, LOCK | Go |
18h | CLB_LUT4_IN3 | LUT4_0/1/2 IN3 input source | EALLOW, LOCK | Go |
1Ch | CLB_FSM_LUT_FN1_0 | LUT function for FSM Unit 1 and Unit 0 | EALLOW, LOCK | Go |
1Eh | CLB_FSM_LUT_FN2 | LUT function for FSM Unit 2 | EALLOW, LOCK | Go |
20h | CLB_LUT4_FN1_0 | LUT function for LUT4 block of Unit 1 and 0 | EALLOW, LOCK | Go |
22h | CLB_LUT4_FN2 | LUT function for LUT4 block of Unit 2 | EALLOW, LOCK | Go |
24h | CLB_FSM_NEXT_STATE_0 | FSM Next state equations for Unit 0 | EALLOW, LOCK | Go |
26h | CLB_FSM_NEXT_STATE_1 | FSM Next state equations for Unit 1 | EALLOW, LOCK | Go |
28h | CLB_FSM_NEXT_STATE_2 | FSM Next state equations for Unit 2 | EALLOW, LOCK | Go |
2Ah | CLB_MISC_CONTROL | Static controls for Ctr,FSM | EALLOW, LOCK | Go |
2Ch | CLB_OUTPUT_LUT_0 | Inp Sel, LUT fns for Out0 | EALLOW, LOCK | Go |
2Eh | CLB_OUTPUT_LUT_1 | Inp Sel, LUT fns for Out1 | EALLOW, LOCK | Go |
30h | CLB_OUTPUT_LUT_2 | Inp Sel, LUT fns for Out2 | EALLOW, LOCK | Go |
32h | CLB_OUTPUT_LUT_3 | Inp Sel, LUT fns for Out3 | EALLOW, LOCK | Go |
34h | CLB_OUTPUT_LUT_4 | Inp Sel, LUT fns for Out4 | EALLOW, LOCK | Go |
36h | CLB_OUTPUT_LUT_5 | Inp Sel, LUT fns for Out5 | EALLOW, LOCK | Go |
38h | CLB_OUTPUT_LUT_6 | Inp Sel, LUT fns for Out6 | EALLOW, LOCK | Go |
3Ah | CLB_OUTPUT_LUT_7 | Inp Sel, LUT fns for Out7 | EALLOW, LOCK | Go |
3Ch | CLB_HLC_EVENT_SEL | Event Selector register for the High Level controller | EALLOW, LOCK | Go |
Complex bit access types are encoded to fit into small table cells. Table 24-16 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
CLB_COUNT_RESET is shown in Figure 24-16 and described in Table 24-17.
Return to the Summary Table.
Counter Block RESET
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | Counter reset select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | Counter reset select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | Counter reset select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_COUNT_MODE_1 is shown in Figure 24-17 and described in Table 24-18.
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Counter Block MODE_1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | Counter MODE_1 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | Counter MODE_1 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | Counter MODE_1 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_COUNT_MODE_0 is shown in Figure 24-18 and described in Table 24-19.
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Counter Block MODE_0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | Counter MODE_0 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | Counter MODE_0 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | Counter MODE_0 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_COUNT_EVENT is shown in Figure 24-19 and described in Table 24-20.
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Counter Block EVENT
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | Counter event select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | Counter event select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | Counter event select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_FSM_EXTRA_IN0 is shown in Figure 24-20 and described in Table 24-21.
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FSM Extra EXT_IN0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | FSM block extra external IN0 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | FSM block extra external IN0 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | FSM block extra external IN0 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_FSM_EXTERNAL_IN0 is shown in Figure 24-21 and described in Table 24-22.
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FSM EXT_IN0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | FSM block EXT_IN0 select input for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | FSM block EXT_IN0 select input for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | FSM block EXT_IN0 select input for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_FSM_EXTERNAL_IN1 is shown in Figure 24-22 and described in Table 24-23.
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FSM_EXT_IN1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | FSM block EXT_IN1 select input for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | FSM block EXT_IN1 select input for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | FSM block EXT_IN1 select input for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_FSM_EXTRA_IN1 is shown in Figure 24-23 and described in Table 24-24.
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FSM Extra_EXT_IN1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | FSM block extra external IN1 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | FSM block extra external IN1 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | FSM block extra external IN1 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_LUT4_IN0 is shown in Figure 24-24 and described in Table 24-25.
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LUT4_0/1/2 IN0 input source
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | LUT4 block IN0 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | LUT4 block IN0 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | LUT4 block IN0 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_LUT4_IN1 is shown in Figure 24-25 and described in Table 24-26.
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LUT4_0/1/2 IN1 input source
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | LUT4 block IN1 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | LUT4 block IN1 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | LUT4 block IN1 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_LUT4_IN2 is shown in Figure 24-26 and described in Table 24-27.
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LUT4_0/1/2 IN2 input source
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | LUT4 block IN2 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | LUT4 block IN2 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | LUT4 block IN2 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_LUT4_IN3 is shown in Figure 24-27 and described in Table 24-28.
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LUT4_0/1/2 IN3 input source
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SEL_2 | SEL_1 | SEL_0 | ||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R/W1C | 0h | Reserved |
14-10 | SEL_2 | R/W | 0h | LUT4 block IN3 select inputs for unit 2. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | SEL_1 | R/W | 0h | LUT4 block IN3 select inputs for unit 1. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | SEL_0 | R/W | 0h | LUT4 block IN3 select inputs for unit 0. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_FSM_LUT_FN1_0 is shown in Figure 24-28 and described in Table 24-29.
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LUT function for FSM Unit 1 and Unit 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FN1 | FN0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FN1 | R/W | 0h | FSM block LUT output function for unit 1 Reset type: SYSRSn |
15-0 | FN0 | R/W | 0h | FSM block LUT output function for unit 0 Reset type: SYSRSn |
CLB_FSM_LUT_FN2 is shown in Figure 24-29 and described in Table 24-30.
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LUT function for FSM Unit 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN1 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W1C | 0h | Reserved |
15-0 | FN1 | R/W | 0h | LUT4 output function for unit 2 Reset type: SYSRSn |
CLB_LUT4_FN1_0 is shown in Figure 24-30 and described in Table 24-31.
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LUT function for LUT4 block of Unit 1 and 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FN1 | FN0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | FN1 | R/W | 0h | LUT4 output function for unit 1 Reset type: SYSRSn |
15-0 | FN0 | R/W | 0h | LUT4 output function for unit 0 Reset type: SYSRSn |
CLB_LUT4_FN2 is shown in Figure 24-31 and described in Table 24-32.
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LUT function for LUT4 block of Unit 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN1 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W1C | 0h | Reserved |
15-0 | FN1 | R/W | 0h | LUT4 output function for unit 2 Reset type: SYSRSn |
CLB_FSM_NEXT_STATE_0 is shown in Figure 24-32 and described in Table 24-33.
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FSM Next state equations for Unit 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S1 | S0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | S1 | R/W | 0h | FSM next state function for S1, unit0 Reset type: SYSRSn |
15-0 | S0 | R/W | 0h | FSM next state function for S0, unit0 Reset type: SYSRSn |
CLB_FSM_NEXT_STATE_1 is shown in Figure 24-33 and described in Table 24-34.
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FSM Next state equations for Unit 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S1 | S0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | S1 | R/W | 0h | FSM next state function for S1, unit1 Reset type: SYSRSn |
15-0 | S0 | R/W | 0h | FSM next state function for S0, unit1 Reset type: SYSRSn |
CLB_FSM_NEXT_STATE_2 is shown in Figure 24-34 and described in Table 24-35.
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FSM Next state equations for Unit 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S1 | S0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | S1 | R/W | 0h | FSM next state function for S1, unit2 Reset type: SYSRSn |
15-0 | S0 | R/W | 0h | FSM next state function for S0, unit2 Reset type: SYSRSn |
CLB_MISC_CONTROL is shown in Figure 24-35 and described in Table 24-36.
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Static controls for Ctr,FSM
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | FSM_EXTRA_SEL1_2 | FSM_EXTRA_SEL0_2 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FSM_EXTRA_SEL1_1 | FSM_EXTRA_SEL0_1 | FSM_EXTRA_SEL1_0 | FSM_EXTRA_SEL0_0 | RESERVED | COUNT_EVENT_CTRL_2 | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT_DIR_2 | COUNT_ADD_SHIFT_2 | COUNT_EVENT_CTRL_1 | COUNT_DIR_1 | COUNT_ADD_SHIFT_1 | COUNT_EVENT_CTRL_0 | COUNT_DIR_0 | COUNT_ADD_SHIFT_0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | FSM_EXTRA_SEL1_2 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 2 0 = Selects State S1 for the FSM LUT 1 = Selects EXTRA_EXT_IN1 for the FSM LUT Reset type: SYSRSn |
16 | FSM_EXTRA_SEL0_2 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 2 0 = Selects State S0 for the FSM LUT 1 = Selects EXTRA_EXT_IN0 for the FSM LUT Reset type: SYSRSn |
15 | FSM_EXTRA_SEL1_1 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 1 0 = Selects State S1 for the FSM LUT 1 = Selects EXTRA_EXT_IN1 for the FSM LUT Reset type: SYSRSn |
14 | FSM_EXTRA_SEL0_1 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 1 0 = Selects State S0 for the FSM LUT 1 = Selects EXTRA_EXT_IN0 for the FSM LUT Reset type: SYSRSn |
13 | FSM_EXTRA_SEL1_0 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 0 0 = Selects State S1 for the FSM LUT 1 = Selects EXTRA_EXT_IN1 for the FSM LUT Reset type: SYSRSn |
12 | FSM_EXTRA_SEL0_0 | R/W | 0h | Defines which input should be selected for the FSM LUT of UNIT 0 0 = Selects State S0 for the FSM LUT 1 = Selects EXTRA_EXT_IN0 for the FSM LUT Reset type: SYSRSn |
11-9 | RESERVED | R-0 | 0h | Reserved |
8 | COUNT_EVENT_CTRL_2 | R/W | 0h | Controls the actions on an EVENT for UNIT2. Must be 0 for indirect loads and HLC loads of the counter to take effect. 0 = No add or shift, but load the predefined value 1 = Based on other bits, add/shift with the predefined value Reset type: SYSRSn |
7 | COUNT_DIR_2 | R/W | 0h | Controls add/shift direction for UNIT 2 0 = right shift or subtract 1 = left shift or add Reset type: SYSRSn |
6 | COUNT_ADD_SHIFT_2 | R/W | 0h | Controls whether the UNIT 2 counter will do an ADD or a SHIFT on an EVENT. 0 =Shift 1 = ADD Reset type: SYSRSn |
5 | COUNT_EVENT_CTRL_1 | R/W | 0h | Controls the actions on an EVENT for UNIT1. Must be 0 for indirect loads and HLC loads of the counter to take effect. 0 = No add or shift, but load the predefined value 1 = Based on other bits, add/shift with the predefined value Reset type: SYSRSn |
4 | COUNT_DIR_1 | R/W | 0h | Controls add/shift direction for UNIT 1 0 = right shift or subtract 1 = left shift or add Reset type: SYSRSn |
3 | COUNT_ADD_SHIFT_1 | R/W | 0h | Controls whether the UNIT 1 counter will do an ADD or a SHIFT on an EVENT. 0 = Shift 1 = ADD Reset type: SYSRSn |
2 | COUNT_EVENT_CTRL_0 | R/W | 0h | Controls the actions on an EVENT for UNIT1. Must be 0 for indirect loads and HLC loads of the counter to take effect. 0 = No add or shift, but load the predefined value 1 = Based on other bits, add/shift with the predefined value Reset type: SYSRSn |
1 | COUNT_DIR_0 | R/W | 0h | Controls add/shift direction for UNIT 0 0 = right shift or subtract 1 = left shift or add Reset type: SYSRSn |
0 | COUNT_ADD_SHIFT_0 | R/W | 0h | Controls whether the UNIT 0 counter will do an ADD or a SHIFT on an EVENT. 0 = Shift 1 = ADD Reset type: SYSRSn |
CLB_OUTPUT_LUT_0 is shown in Figure 24-36 and described in Table 24-37.
Return to the Summary Table.
Inp Sel, LUT fns for Out0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_1 is shown in Figure 24-37 and described in Table 24-38.
Return to the Summary Table.
Inp Sel, LUT fns for Out1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_2 is shown in Figure 24-38 and described in Table 24-39.
Return to the Summary Table.
Inp Sel, LUT fns for Out2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_3 is shown in Figure 24-39 and described in Table 24-40.
Return to the Summary Table.
Inp Sel, LUT fns for Out3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_4 is shown in Figure 24-40 and described in Table 24-41.
Return to the Summary Table.
Inp Sel, LUT fns for Out4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_5 is shown in Figure 24-41 and described in Table 24-42.
Return to the Summary Table.
Inp Sel, LUT fns for Out5
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_6 is shown in Figure 24-42 and described in Table 24-43.
Return to the Summary Table.
Inp Sel, LUT fns for Out6
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_OUTPUT_LUT_7 is shown in Figure 24-43 and described in Table 24-44.
Return to the Summary Table.
Inp Sel, LUT fns for Out7
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FN | IN2 | IN1 | IN0 | |||||||||||||||||||||||||||
R/W1C-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R/W1C | 0h | Reserved |
22-15 | FN | R/W | 0h | Output function for output LUT Reset type: SYSRSn |
14-10 | IN2 | R/W | 0h | Select value for IN2 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | IN1 | R/W | 0h | Select value for IN1 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | IN0 | R/W | 0h | Select value for IN0 of output LUT. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
CLB_HLC_EVENT_SEL is shown in Figure 24-44 and described in Table 24-45.
Return to the Summary Table.
Event Selector register for the High Level controller
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EVENT3_SEL | ||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EVENT3_SEL | EVENT2_SEL | EVENT1_SEL | EVENT0_SEL | ||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19-15 | EVENT3_SEL | R/W | 0h | 5 bit select value for EVENT3 of the High Level Controller. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
14-10 | EVENT2_SEL | R/W | 0h | 5 bit select value for EVENT2 of the High Level Controller. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
9-5 | EVENT1_SEL | R/W | 0h | 5 bit select value for EVENT1 of the High Level Controller. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |
4-0 | EVENT0_SEL | R/W | 0h | 5 bit select value for EVENT0 of the High Level Controller. See the Static Switch Block Output Mux Table. Reset type: SYSRSn |