SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Table 13-13 lists the memory-mapped registers for the SDFM_REGS registers. All register offset addresses not listed in Table 13-13 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | SDIFLG | Interrupt Flag Register | Go | |
2h | SDIFLGCLR | Interrupt Flag Clear Register | Go | |
4h | SDCTL | SD Control Register | EALLOW | Go |
6h | SDMFILEN | SD Master Filter Enable | EALLOW | Go |
10h | SDCTLPARM1 | Control Parameter Register for Ch1 | EALLOW | Go |
11h | SDDFPARM1 | Data Filter Parameter Register for Ch1 | EALLOW | Go |
12h | SDDPARM1 | Integer Parameter Register for Ch1 | EALLOW | Go |
13h | SDCMPH1 | High-level Threshold Register for Ch1 | EALLOW | Go |
14h | SDCMPL1 | Low-level Threshold Register for Ch1 | EALLOW | Go |
15h | SDCPARM1 | Comparator Parameter Register for Ch1 | EALLOW | Go |
16h | SDDATA1 | Filter Data Register (16 or 32bit) for Ch1 | Go | |
20h | SDCTLPARM2 | Control Parameter Register for Ch2 | EALLOW | Go |
21h | SDDFPARM2 | Data Filter Parameter Register for Ch2 | EALLOW | Go |
22h | SDDPARM2 | Integer Parameter Register for Ch2 | EALLOW | Go |
23h | SDCMPH2 | High-level Threshold Register for Ch2 | EALLOW | Go |
24h | SDCMPL2 | Low-level Threshold Register for Ch2 | EALLOW | Go |
25h | SDCPARM2 | Comparator Parameter Register for Ch2 | EALLOW | Go |
26h | SDDATA2 | Filter Data Register (16 or 32bit) for Ch2 | Go | |
30h | SDCTLPARM3 | Control Parameter Register for Ch3 | EALLOW | Go |
31h | SDDFPARM3 | Data Filter Parameter Register for Ch3 | EALLOW | Go |
32h | SDDPARM3 | Integer Parameter Register for Ch3 | EALLOW | Go |
33h | SDCMPH3 | High-level Threshold Register for Ch3 | EALLOW | Go |
34h | SDCMPL3 | Low-level Threshold Register for Ch3 | EALLOW | Go |
35h | SDCPARM3 | Comparator Parameter Register for Ch3 | EALLOW | Go |
36h | SDDATA3 | Filter Data Register (16 or 32bit) for Ch3 | Go | |
40h | SDCTLPARM4 | Control Parameter Register for Ch4 | EALLOW | Go |
41h | SDDFPARM4 | Data Filter Parameter Register for Ch4 | EALLOW | Go |
42h | SDDPARM4 | Integer Parameter Register for Ch4 | EALLOW | Go |
43h | SDCMPH4 | High-level Threshold Register for Ch4 | EALLOW | Go |
44h | SDCMPL4 | Low-level Threshold Register for Ch4 | EALLOW | Go |
45h | SDCPARM4 | Comparator Parameter Register for Ch4 | EALLOW | Go |
46h | SDDATA4 | Filter Data Register (16 or 32bit) for Ch4 | Go |
Complex bit access types are encoded to fit into small table cells. Table 13-14 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
SDIFLG is shown in Figure 13-11 and described in Table 13-15.
Return to the Summary Table.
Interrupt Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MIF | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AF4 | AF3 | AF2 | AF1 | MF4 | MF3 | MF2 | MF1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IFL4 | IFH4 | IFL3 | IFH3 | IFL2 | IFH2 | IFL1 | IFH1 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | MIF | R | 0h | Set whenever any interrupt (ACK1-4, MF1-4,IFL1-4,IFH1-4) is active Reset type: SYSRSn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15 | AF4 | R | 0h | 0: No new data available from Filter 4 1: New data available from Filter 4 Reset type: SYSRSn |
14 | AF3 | R | 0h | 0: No new data available from Filter 3 1: New data available from Filter 3 Reset type: SYSRSn |
13 | AF2 | R | 0h | 0: No new data available from Filter 2 1: New data available from Filter 2 Reset type: SYSRSn |
12 | AF1 | R | 0h | 0: No new data available from Filter 1 1: New data available from Filter 1 Reset type: SYSRSn |
11 | MF4 | R | 0h | 0: Modulator is operating normally for Filter 4 1: Modulator failure for Filter 4 Reset type: SYSRSn |
10 | MF3 | R | 0h | 0: Modulator is operating normally for Filter 3 1: Modulator failure for Filter 3 Reset type: SYSRSn |
9 | MF2 | R | 0h | 0: Modulator is operating normally for Filter 2 1: Modulator failure for Filter 2 Reset type: SYSRSn |
8 | MF1 | R | 0h | 0: Modulator is operating normally for Filter 1 1: Modulator failure for Filter 1 Reset type: SYSRSn |
7 | IFL4 | R | 0h | 0: Comparator Filter 4 output is above the low limit threshold 1: Comparator Filter 4 output is equal to or below the low level threshold, if enabled Reset type: SYSRSn |
6 | IFH4 | R | 0h | 0: Comparator Filter 4 output is below the high limit threshold 1: Comparator Filter 4 output is equal to or above the high level threshold, if enabled Reset type: SYSRSn |
5 | IFL3 | R | 0h | 0: Comparator Filter 3 output is above the low limit threshold 1: Comparator Filter 3 output is equal to or below the low level threshold, if enabled Reset type: SYSRSn |
4 | IFH3 | R | 0h | 0: Comparator Filter 3 output is below the high limit threshold 1: Comparator Filter 3 output is equal to or above the high level threshold, if enabled Reset type: SYSRSn |
3 | IFL2 | R | 0h | 0: Comparator Filter 2 output is above the low limit threshold 1: Comparator Filter 2 output is equal to or below the low level threshold, if enabled Reset type: SYSRSn |
2 | IFH2 | R | 0h | 0: Comparator Filter 2 output is below the high limit threshold 1: Comparator Filter 2 output is equal to or above the high level threshold, if enabled Reset type: SYSRSn |
1 | IFL1 | R | 0h | 0: Comparator Filter 1 output is above the low limit threshold 1: Comparator Filter 1 output is equal to or below the low level threshold, if enabled Reset type: SYSRSn |
0 | IFH1 | R | 0h | 0: Comparator Filter 1 output is below the high limit threshold 1: Comparator Filter 1 output is equal to or above the high level threshold, if enabled Reset type: SYSRSn |
SDIFLGCLR is shown in Figure 13-12 and described in Table 13-16.
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Interrupt Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MIF | RESERVED | ||||||
R-0/W1S-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AF4 | AF3 | AF2 | AF1 | MF4 | MF3 | MF2 | MF1 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IFL4 | IFH4 | IFL3 | IFH3 | IFL2 | IFH2 | IFL1 | IFH1 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | MIF | R-0/W1S | 0h | Flag-clear bit for SDFM Master Interrupt flag. Write 1 to clear MIF. Writes of '0' are ignored. Note: If the MIF flag is cleared and other Interrupts are still pending, MIF will again be set to 1 on the following SysClk cycle, and the INT output will be reasserted (pulsed low) Reset type: SYSRSn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15 | AF4 | R-0/W1S | 0h | SD Module Interrupt Flag Clear Bits: Writing a '1' will clear the respective flag bit in the SDINTFLG register. Writes of '0' are ignored. Note: If user writes a '1' to clear a bit on the same cycle that the hardware is trying to set the bit to '1', then hardware has priority and the bit will not be cleared. Flag-clear bit for Acknowledge flag for Filter 4 Reset type: SYSRSn |
14 | AF3 | R-0/W1S | 0h | Flag-clear bit for Acknowledge flag for Filter 3 Reset type: SYSRSn |
13 | AF2 | R-0/W1S | 0h | Flag-clear bit for Acknowledge flag for Filter 2 Reset type: SYSRSn |
12 | AF1 | R-0/W1S | 0h | Flag-clear bit for Acknowledge flag for Filter 1 Reset type: SYSRSn |
11 | MF4 | R-0/W1S | 0h | Flag-clear bit for Modulator Failure for Filter 4 Reset type: SYSRSn |
10 | MF3 | R-0/W1S | 0h | Flag-clear bit for Modulator Failure for Filter 3 Reset type: SYSRSn |
9 | MF2 | R-0/W1S | 0h | Flag-clear bit for Modulator Failure for Filter 2 Reset type: SYSRSn |
8 | MF1 | R-0/W1S | 0h | Flag-clear bit for Modulator Failure for Filter 1 Reset type: SYSRSn |
7 | IFL4 | R-0/W1S | 0h | Flag-clear bit for Low-Level Interrupt flag Filter 4 Reset type: SYSRSn |
6 | IFH4 | R-0/W1S | 0h | Flag-clear bit for High-level Interrupt flag Filter 4 Reset type: SYSRSn |
5 | IFL3 | R-0/W1S | 0h | Flag-clear bit for Low-Level Interrupt flag Filter 3 Reset type: SYSRSn |
4 | IFH3 | R-0/W1S | 0h | Flag-clear bit for High-level Interrupt flag Filter 3 Reset type: SYSRSn |
3 | IFL2 | R-0/W1S | 0h | Flag-clear bit for Low-Level Interrupt flag Filter 2 Reset type: SYSRSn |
2 | IFH2 | R-0/W1S | 0h | Flag-clear bit for High-level Interrupt flag Filter 2 Reset type: SYSRSn |
1 | IFL1 | R-0/W1S | 0h | Flag-clear bit for Low-Level Interrupt flag Filter 1 Reset type: SYSRSn |
0 | IFH1 | R-0/W1S | 0h | Flag-clear bit for High-level Interrupt flag Filter 1 Reset type: SYSRSn |
SDCTL is shown in Figure 13-13 and described in Table 13-17.
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SD Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | MIE | RESERVED | ||||
R-0-0h | R-0-0h | R/W-0h | R-0-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R-0-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14 | RESERVED | R-0 | 0h | Reserved |
13 | MIE | R/W | 0h | Master interrupt enable. 0: Interrupt pin and interrupt flags are blocked (interrupt pin INT always inactive). 1: Interrupt pin and interrupt flags are not blocked and can be set and reset (if individually enabled). Reset type: SYSRSn |
12-0 | RESERVED | R-0 | 0h | Reserved |
SDMFILEN is shown in Figure 13-14 and described in Table 13-18.
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SD Master Filter Enable
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | MFE | RESERVED | RESERVED | RESERVED | ||
R-0-0h | R-0-0h | R/W-0h | R-0-0h | R-0-0h | R-0-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R-0-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R-0 | 0h | Reserved |
12 | RESERVED | R-0 | 0h | Reserved |
11 | MFE | R/W | 0h | Master Filter Enable. Functionally AND'ed with bit FEN in the Data Filter Parameter Register 0: Data filter units of all filter modules are disabled. 1: Data filter units can be enabled if bit FEN is '1'. Reset type: SYSRSn |
10 | RESERVED | R-0 | 0h | Reserved |
9 | RESERVED | R-0 | 0h | Reserved |
8-7 | RESERVED | R-0 | 0h | Reserved |
6-4 | RESERVED | R-0 | 0h | Reserved |
3-0 | RESERVED | R-0 | 0h | Reserved |
SDCTLPARM1 is shown in Figure 13-15 and described in Table 13-19.
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Control Parameter Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | MOD | |||
R-0h | R-0-0h | R-0-0h | R-0-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | MOD | R/W | 0h | Delta-Sigma Modulator mode 00: The clock speed is equal to the data rate from the modulator 01: The clock rate is half of the data rate from the modulator 10: The data from the modulator is Manchester decoded 11: The clock rate is twice the data rate of the modulator Reset type: SYSRSn |
SDDFPARM1 is shown in Figure 13-16 and described in Table 13-20.
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Data Filter Parameter Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SDSYNCEN | SST | AE | FEN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DOSR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12 | SDSYNCEN | R/W | 0h | Data Filter Reset enable for External Reset typ from PWM Compare output. 0: Data filter cannot be reset by external PWM compare output 1: Data filter can be reset by external PWM compare output Reset type: SYSRSn |
11-10 | SST | R/W | 0h | Data filter structure. 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure Reset type: SYSRSn |
9 | AE | R/W | 0h | Acknowledge enable. 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter Reset type: SYSRSn |
8 | FEN | R/W | 0h | Filter enable. 0: The filter is disabled and no data is produced 1: The filter is enabled and data are produced in the Data filter Reset type: SYSRSn |
7-0 | DOSR | R/W | 0h | Oversampling ratio. The actual rate is DOSR + 1. These bits set the oversampling ratio of the filter. 0x0FF represents an oversampling ratio of 256. Reset type: SYSRSn |
SDDPARM1 is shown in Figure 13-17 and described in Table 13-21.
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Integer Parameter Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SH | DR | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | SH | R/W | 0h | Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen. Reset type: SYSRSn |
10 | DR | R/W | 0h | Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R-0 | 0h | Reserved |
6-0 | RESERVED | R/W | 0h | Reserved |
SDCMPH1 is shown in Figure 13-18 and described in Table 13-22.
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High-level Threshold Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | HLT | R/W | 0h | Unsigned high-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCMPL1 is shown in Figure 13-19 and described in Table 13-23.
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Low-level Threshold Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | LLT | R/W | 0h | Unsigned low-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCPARM1 is shown in Figure 13-20 and described in Table 13-24.
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Comparator Parameter Register for Ch1
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MFIE | CS1_CS0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS1_CS0 | IEL | IEH | COSR | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R-0 | 0h | Reserved |
9 | MFIE | R/W | 0h | 0: The modulator failure flag as well as the output INT is disabled for this particular flag 1: The modulator failure flag is enabled Reset type: SYSRSn |
8-7 | CS1_CS0 | R/W | 0h | Comparator filter structure. 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure Reset type: SYSRSn |
6 | IEL | R/W | 0h | Low-level interrupt enable. 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag 1: The low-level interrupt flag is enabled Reset type: SYSRSn |
5 | IEH | R/W | 0h | High-level interrupt enable. 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag 1: The high-level interrupt flag is enabled Reset type: SYSRSn |
4-0 | COSR | R/W | 0h | Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 31. Reset type: SYSRSn |
SDDATA1 is shown in Figure 13-21 and described in Table 13-25.
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Filter Data Register (16 or 32bit) for Ch1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA32HI | DATA16 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DATA32HI | R | 0h | Hi-order 16b in 32b mode, 16-bit Data in 16b mode Reset type: SYSRSn |
15-0 | DATA16 | R | 0h | Lo-order 16b in 32b mode Reset type: SYSRSn |
SDCTLPARM2 is shown in Figure 13-22 and described in Table 13-26.
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Control Parameter Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | MOD | |||
R-0h | R-0-0h | R-0-0h | R-0-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | MOD | R/W | 0h | Delta-Sigma Modulator mode 00: The clock speed is equal to the data rate from the modulator 01: The clock rate is half of the data rate from the modulator 10: The data from the modulator is Manchester decoded 11: The clock rate is twice the data rate of the modulator Reset type: SYSRSn |
SDDFPARM2 is shown in Figure 13-23 and described in Table 13-27.
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Data Filter Parameter Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SDSYNCEN | SST | AE | FEN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DOSR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12 | SDSYNCEN | R/W | 0h | Data Filter Reset enable for External Reset typ from PWM Compare output. 0: Data filter cannot be reset by external PWM compare output 1: Data filter can be reset by external PWM compare output Reset type: SYSRSn |
11-10 | SST | R/W | 0h | Data filter structure. 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure Reset type: SYSRSn |
9 | AE | R/W | 0h | Acknowledge enable. 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter Reset type: SYSRSn |
8 | FEN | R/W | 0h | Filter enable. 0: The filter is disabled and no data is produced 1: The filter is enabled and data are produced in the Data filter Reset type: SYSRSn |
7-0 | DOSR | R/W | 0h | Oversampling ratio. The actual rate is DOSR + 1. These bits set the oversampling ratio of the filter. 0x0FF represents an oversampling ratio of 256. Reset type: SYSRSn |
SDDPARM2 is shown in Figure 13-24 and described in Table 13-28.
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Integer Parameter Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SH | DR | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | SH | R/W | 0h | Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen. Reset type: SYSRSn |
10 | DR | R/W | 0h | Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R-0 | 0h | Reserved |
6-0 | RESERVED | R/W | 0h | Reserved |
SDCMPH2 is shown in Figure 13-25 and described in Table 13-29.
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High-level Threshold Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | HLT | R/W | 0h | Unsigned high-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCMPL2 is shown in Figure 13-26 and described in Table 13-30.
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Low-level Threshold Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | LLT | R/W | 0h | Unsigned low-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCPARM2 is shown in Figure 13-27 and described in Table 13-31.
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Comparator Parameter Register for Ch2
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MFIE | CS1_CS0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS1_CS0 | IEL | IEH | COSR | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R-0 | 0h | Reserved |
9 | MFIE | R/W | 0h | 0: The modulator failure flag as well as the output INT is disabled for this particular flag 1: The modulator failure flag is enabled Reset type: SYSRSn |
8-7 | CS1_CS0 | R/W | 0h | Comparator filter structure. 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure Reset type: SYSRSn |
6 | IEL | R/W | 0h | Low-level interrupt enable. 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag 1: The low-level interrupt flag is enabled Reset type: SYSRSn |
5 | IEH | R/W | 0h | High-level interrupt enable. 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag 1: The high-level interrupt flag is enabled Reset type: SYSRSn |
4-0 | COSR | R/W | 0h | Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 31. Reset type: SYSRSn |
SDDATA2 is shown in Figure 13-28 and described in Table 13-32.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA32HI | DATA16 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DATA32HI | R | 0h | Hi-order 16b in 32b mode, 16-bit Data in 16b mode Reset type: SYSRSn |
15-0 | DATA16 | R | 0h | Lo-order 16b in 32b mode Reset type: SYSRSn |
SDCTLPARM3 is shown in Figure 13-29 and described in Table 13-33.
Return to the Summary Table.
Control Parameter Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | MOD | |||
R-0h | R-0-0h | R-0-0h | R-0-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | MOD | R/W | 0h | Delta-Sigma Modulator mode 00: The clock speed is equal to the data rate from the modulator 01: The clock rate is half of the data rate from the modulator 10: The data from the modulator is Manchester decoded 11: The clock rate is twice the data rate of the modulator Reset type: SYSRSn |
SDDFPARM3 is shown in Figure 13-30 and described in Table 13-34.
Return to the Summary Table.
Data Filter Parameter Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SDSYNCEN | SST | AE | FEN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DOSR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12 | SDSYNCEN | R/W | 0h | Data Filter Reset enable for External Reset typ from PWM Compare output. 0: Data filter cannot be reset by external PWM compare output 1: Data filter can be reset by external PWM compare output Reset type: SYSRSn |
11-10 | SST | R/W | 0h | Data filter structure. 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure Reset type: SYSRSn |
9 | AE | R/W | 0h | Acknowledge enable. 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter Reset type: SYSRSn |
8 | FEN | R/W | 0h | Filter enable. 0: The filter is disabled and no data is produced 1: The filter is enabled and data are produced in the data filter Reset type: SYSRSn |
7-0 | DOSR | R/W | 0h | Oversampling ratio. The actual rate is DOSR + 1. These bits set the oversampling ratio of the filter. 0x0FF represents an oversampling ratio of 256. Reset type: SYSRSn |
SDDPARM3 is shown in Figure 13-31 and described in Table 13-35.
Return to the Summary Table.
Integer Parameter Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SH | DR | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | SH | R/W | 0h | Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen. Reset type: SYSRSn |
10 | DR | R/W | 0h | Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R-0 | 0h | Reserved |
6-0 | RESERVED | R/W | 0h | Reserved |
SDCMPH3 is shown in Figure 13-32 and described in Table 13-36.
Return to the Summary Table.
High-level Threshold Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | HLT | R/W | 0h | Unsigned high-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCMPL3 is shown in Figure 13-33 and described in Table 13-37.
Return to the Summary Table.
Low-level Threshold Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | LLT | R/W | 0h | Unsigned low-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCPARM3 is shown in Figure 13-34 and described in Table 13-38.
Return to the Summary Table.
Comparator Parameter Register for Ch3
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MFIE | CS1_CS0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS1_CS0 | IEL | IEH | COSR | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R-0 | 0h | Reserved |
9 | MFIE | R/W | 0h | 0: The modulator failure flag as well as the output INT is disabled for this particular flag 1: The modulator failure flag is enabled Reset type: SYSRSn |
8-7 | CS1_CS0 | R/W | 0h | Comparator filter structure. 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure Reset type: SYSRSn |
6 | IEL | R/W | 0h | Low-level interrupt enable. 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag 1: The low-level interrupt flag is enabled Reset type: SYSRSn |
5 | IEH | R/W | 0h | High-level interrupt enable. 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag 1: The high-level interrupt flag is enabled Reset type: SYSRSn |
4-0 | COSR | R/W | 0h | Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 31. Reset type: SYSRSn |
SDDATA3 is shown in Figure 13-35 and described in Table 13-39.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch3
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA32HI | DATA16 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DATA32HI | R | 0h | Hi-order 16b in 32b mode, 16-bit Data in 16b mode Reset type: SYSRSn |
15-0 | DATA16 | R | 0h | Lo-order 16b in 32b mode Reset type: SYSRSn |
SDCTLPARM4 is shown in Figure 13-36 and described in Table 13-40.
Return to the Summary Table.
Control Parameter Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | MOD | |||
R-0h | R-0-0h | R-0-0h | R-0-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | MOD | R/W | 0h | Delta-Sigma Modulator mode 00: The clock speed is equal to the data rate from the modulator 01: The clock rate is half of the data rate from the modulator 10: The data from the modulator is Manchester decoded 11: The clock rate is twice the data rate of the modulator Reset type: SYSRSn |
SDDFPARM4 is shown in Figure 13-37 and described in Table 13-41.
Return to the Summary Table.
Data Filter Parameter Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SDSYNCEN | SST | AE | FEN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DOSR | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-13 | RESERVED | R | 0h | Reserved |
12 | SDSYNCEN | R/W | 0h | Data Filter Reset enable for External Reset typ from PWM Compare output. 0: Data filter cannot be reset by external PWM compare output 1: Data filter can be reset by external PWM compare output Reset type: SYSRSn |
11-10 | SST | R/W | 0h | Data filter structure. 00: Data filter runs with a Sincfast structure 01: Data filter runs with a Sinc1 structure 10: Data filter runs with a Sinc2 structure 11: Data filter runs with a Sinc3 structure Reset type: SYSRSn |
9 | AE | R/W | 0h | Acknowledge enable. 0: Acknowledge flag is disabled for the particular filter 1: Acknowledge flag is enabled for the particular filter Reset type: SYSRSn |
8 | FEN | R/W | 0h | Filter enable. 0: The filter is disabled and no data is produced 1: The filter is enabled and data are produced in the sinc filter Reset type: SYSRSn |
7-0 | DOSR | R/W | 0h | Oversampling ratio. The actual rate is DOSR + 1. These bits set the oversampling ratio of the filter. 0x0FF represents an oversampling ratio of 256. Reset type: SYSRSn |
SDDPARM4 is shown in Figure 13-38 and described in Table 13-42.
Return to the Summary Table.
Integer Parameter Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SH | DR | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | SH | R/W | 0h | Shift Control These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data representation is chosen. Reset type: SYSRSn |
10 | DR | R/W | 0h | Data representation 0: Data stored in 16b 2's complement 1: Data stored in 32b 2's complement Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R-0 | 0h | Reserved |
6-0 | RESERVED | R/W | 0h | Reserved |
SDCMPH4 is shown in Figure 13-39 and described in Table 13-43.
Return to the Summary Table.
High-level Threshold Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | HLT | R/W | 0h | Unsigned high-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCMPL4 is shown in Figure 13-40 and described in Table 13-44.
Return to the Summary Table.
Low-level Threshold Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | LLT | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LLT | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R-0 | 0h | Reserved |
14-0 | LLT | R/W | 0h | Unsigned low-level threshold for the comparator filter output. Reset type: SYSRSn |
SDCPARM4 is shown in Figure 13-41 and described in Table 13-45.
Return to the Summary Table.
Comparator Parameter Register for Ch4
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MFIE | CS1_CS0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CS1_CS0 | IEL | IEH | COSR | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R-0 | 0h | Reserved |
9 | MFIE | R/W | 0h | 0: The modulator failure flag as well as the output INT is disabled for this particular flag 1: The modulator failure flag is enabled Reset type: SYSRSn |
8-7 | CS1_CS0 | R/W | 0h | Comparator filter structure. 00: Comparator filter runs with a sincfast structure 01: Comparator filter runs with a Sinc1 structure 10: Comparator filter runs with a Sinc2 structure 11: Comparator filter runs with a Sinc3 structure Reset type: SYSRSn |
6 | IEL | R/W | 0h | Low-level interrupt enable. 0: The low-level interrupt flag as well as the output INT is disabled for this particular flag 1: The low-level interrupt flag is enabled Reset type: SYSRSn |
5 | IEH | R/W | 0h | High-level interrupt enable. 0: The high-level interrupt flag as well as the output INT is disabled for this particular flag 1: The high-level interrupt flag is enabled Reset type: SYSRSn |
4-0 | COSR | R/W | 0h | Oversampling ratio. The actual rate is COSR + 1. These bits set the oversampling ratio of the filter. 0x1F represents an oversampling ratio of 31. Reset type: SYSRSn |
SDDATA4 is shown in Figure 13-42 and described in Table 13-46.
Return to the Summary Table.
Filter Data Register (16 or 32bit) for Ch4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATA32HI | DATA16 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DATA32HI | R | 0h | Hi-order 16b in 32b mode, 16-bit Data in 16b mode Reset type: SYSRSn |
15-0 | DATA16 | R | 0h | Lo-order 16b in 32b mode Reset type: SYSRSn |