SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The USB receive control and status endpoint n low 8-bit register (USBRXCSRL[n]) provides control and status bits for transfers through the currently selected receive endpoint.
Mode(s): | Host | Device |
The USBCSRL[n] registers in Host mode are shown in Figure 22-46 and described in Table 22-48.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRDT | STALLED | REQPKT | FLUSH | DATAERR / NAKTO | ERROR | FULL | RXRDY |
W1C-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | NAKTO | Clear Data Toggle. | |
0 | No effect | ||
1 | Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register. | ||
6 | STALLED | Endpoint Stalled. Software must clear this bit. | |
0 | No handshake has been received. | ||
1 | A STALL handshake has been received. The EPn bit in the USBRXIS register is also set. | ||
5 | REQPKT | Request Packet. This bit is cleared when the RXRDY bit is set. | |
0 | No request | ||
1 | Requests an IN transaction. | ||
4 | FLUSH | Flush FIFO. If the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. Note:This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. | |
0 | No effect | ||
1 | Flushes the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. | ||
3 | DATAERR / NAKTO | Data Error / NAK Timeout | |
0 | Normal operation | ||
1 | Bulk endpoints only: Indicates that the receive endpoint is halted following the receipt of NAK responses for longer than the time set by the NAKLMT field in the USBRXINTERVAL[n] register. Software must clear this bit to allow the endpoint to continue. | ||
2 | ERROR | Error. Software must clear this bit. Note: This bit is only valid when the receive endpoint is operating in Bulk or Interrupt mode. | |
0 | No error | ||
1 | Three attempts have been made to receive a packet and no data packet has been received. The EPn bit in the USBRXIS register is set in this situation. | ||
1 | FULL | FIFO Full | |
0 | The receive FIFO is not full. | ||
1 | No more packets can be loaded into the receive FIFO. | ||
0 | RXRDY | Receive Packet Ready. If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. | |
0 | No data packet has been received. | ||
1 | Indicates that a data packet has been received. The EPn bit in the USBTXIS register is also set in this situation. |
USBCSRL0 in Device mode is shown in Figure 22-47 and described in Table 22-49.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRDT | STALLED | STALL | FLUSH | Reserved | FULL | RXRDY |
W1C-0 | W1C-0 | R/W-0 | R-0 | R/W-0 | R/W-0 | R/W-0 | R-0 |
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
7 | CLRDT | Clear Data Toggle | |
0 | No effect | ||
1 | Writing a 1 to this bit clears the DT bit in the USBRXCSRH[n] register. | ||
6 | STALLED | Endpoint Stalled. Software must clear this bit. | |
0 | A STALL handshake has been transmitted. | ||
1 | A STALL handshake has been transmitted. | ||
5 | STALL | Send Stall. Software must clear this bit to terminate the STALL condition. | |
0 | No effect | ||
1 | Issues a STALL handshake. | ||
4 | FLUSH | Flush FIFO. The CPU writes a 1 to this bit to flush the next packet to be read from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. Note that if the FIFO is double-buffered, FLUSH may have to be set twice to completely clear the FIFO. | |
0 | No effect | ||
1 | Flushes the next packet from the endpoint receive FIFO. The FIFO pointer is reset and the RXRDY bit is cleared. | ||
Note: This bit should only be set when the RXRDY bit is set. At other times, it may cause data to be corrupted. | |||
3-2 | Reserved | Reserved | |
1 | FULL | FIFO Full | |
0 | The receive FIFO is not full. | ||
1 | No more packets can be loaded into the receive FIFO. | ||
0 | RXRDY | Receive Packet Ready. If the AUTOCLR bit in the USBRXCSRH[n] register is set, then the this bit is automatically cleared when a packet of USBRXMAXP[n] bytes has been unloaded from the receive FIFO. If the AUTOCLR bit is clear, or if packets of less than the maximum packet size are unloaded, then software must clear this bit manually when the packet has been unloaded from the receive FIFO. | |
0 | No data packet has been received. | ||
1 | A data packet has been received. The EPn bit in the USBTXIS register is also set in this situation. | ||
This bit is cleared by writing a 1 to the RXRDYC bit. |