SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The USB maximum transmit data endpoint n 16-bit registers (USBTXMAXP[n]) define the maximum amount of data that can be transferred through the selected transmit endpoint in a single operation.
Bits 10:0 define (in bytes) the maximum payload transmitted in a single transaction. The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for bulk and interrupt transfers in full-speed operation.
The total amount of data represented by the value written to this register must not exceed the FIFO size for the transmit endpoint, and must not exceed half the FIFO size if double-buffering is required.
If this register is changed after packets have been sent from the endpoint, the transmit endpoint FIFO must be completely flushed (using the FLUSH bit in USBTXCSRLn) after writing the new value to this register.
Note: USBTXMAXP[n] must be set to an even number of bytes for proper interrupt generation in DMA Basic Mode.
Mode(s): | Host | Device |
The USBTXMAXP[n] registers are shown in Figure 22-33 and described in Table 22-35.
15 | 11 | 10 | 0 |
Reserved | MAXLOAD |
R-0 | R/W-000 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Value | Description |
---|---|---|---|
15-11 | Reserved | 0 | Reserved |
10-0 | MAXLOAD | Maximum Payload specifies the maximum payload in bytes per transaction. |