SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
Figure 20-22 shows the case where RFULL is set, but the overrun condition is prevented by a read from DRR1 at least 2.5 cycles before the next serial word is completely shifted into RSR1. This makes sure that an RBR1-to-DRR1 copy of word B occurs before receiver attempts to transfer word C from RSR1 to RBR1.