SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
(USBTXIS), offset 0x002
Use caution when reading this register. Performing a read may change bit status.
The USB transmit interrupt status 16-bit read-only register (USBTXIS) indicates which interrupts are currently active for control endpoint 0 and the transmit endpoints 1–15. The meaning of the EPn bits in this register is based on the mode of the device. The EP1 through EP15 bits always indicate that the USB controller is sending data; however, in Host mode, the bits refer to OUT endpoints; while in Device mode, the bits refer to IN endpoints.
Note:The EP0 bit is special in Host and Device modes and indicates that either a control IN or control OUT endpoint has generated an interrupt. Both the control IN and control OUT endpoints are captured in the EP0 bit of the USBTXIS register.
Mode(s): | Host | Device |
USBTXIS is shown in Figure 22-6 and described in Table 22-8.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EP15 | EP14 | EP13 | EP12 | EP11 | EP10 | EP9 | EP8 |
R-0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EP7 | EP6 | EP5 | EP4 | EP3 | EP2 | EP1 | EP0 |
R-0 | |||||||
Bit | Field | Value | Description |
---|---|---|---|
15 | EP15 | TX Endpoint 15 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 15 transmit interrupt is asserted. | ||
14 | EP14 | TX Endpoint 14 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 14 transmit interrupt is asserted. | ||
13 | EP13 | TX Endpoint 13 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 13 transmit interrupt is asserted. | ||
12 | EP12 | TX Endpoint 12 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 12 transmit interrupt is asserted. | ||
11 | EP11 | TX Endpoint 11 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 11 transmit interrupt is asserted. | ||
10 | EP10 | TX Endpoint 10 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 10 transmit interrupt is asserted. | ||
9 | EP9 | TX Endpoint 9 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 9 transmit interrupt is asserted. | ||
8 | EP8 | TX Endpoint 8 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 8 transmit interrupt is asserted. | ||
7 | EP7 | TX Endpoint 7 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 7 transmit interrupt is asserted. | ||
6 | EP6 | TX Endpoint 6 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 6 transmit interrupt is asserted. | ||
5 | EP5 | TX Endpoint 5 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 5 transmit interrupt is asserted. | ||
4 | EP4 | TX Endpoint 4 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 4 transmit interrupt is asserted. | ||
3 | EP3 | TX Endpoint 3 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 3 transmit interrupt is asserted. | ||
2 | EP2 | TX Endpoint 2 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 2 transmit interrupt is asserted. | ||
1 | EP1 | TX Endpoint 1 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 1 transmit interrupt is asserted. | ||
0 | EP0 | TX and RX Endpoint 0 Interrupt | |
0 | No interrupt | ||
1 | The Endpoint 0 transmit and receive interrupt is asserted. |