SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The receive data from the MII interface is stored in the receive data FIFO which is 32 bytes. The PRU can access this data through the register R31. Depending on the configuration settings, the data can be latched on reception of one or two bytes. In each scheme, the configured number of nibbles is assembled before being copied into the PRU registers. Figure 30-52 shows the inputs and outputs of the data latch logic block.
The receiver logic in MII_RT can be programmed through the PRUSS_MII_RT_RXCFG0 and PRUSS_MII_RT_RXCFG1 registers to remove or retain the preamble + SFD from incoming frames.