SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4B23 2000 0x4B2B 2000 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables (PRUSS_MII_RT_RXCFG0) for the RX path. PRUSS_MII_RT_RXCFG0 is attached to PRU0. PRUSS_MII_RT_RXCFG0 controls which RX port is attached to PRU0. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_L2_EOF_SCLR_DIS | RX_ERR_RAW | RX_SFD_RAW | RX_AUTO_FWD_PRE | RX_BYTE_SWAP | RX_L2_EN | RX_MUX_SEL | RX_CUT_PREAMBLE | RX_DATA_RDY_MODE_DIS | RX_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x000000 | |
9 | RX_L2_EOF_SCLR_DIS | 0x0: RX_EOF flag in R31 and RXL2 is self cleared by hardware when RXL2 is enabled 0x1: RX_EOF flag in R31 and RXL2 is not self cleared by hardware when RXL2 is enabled. To clear this flag, RX_EOF_CLR must be set. | RW | 0x0 |
8 | RX_ERR_RAW | 0x0: Error Raw Mode Disabled. RX_ERR is qualified with RX_DV, meaning RX_DV = 1 before RX_ERR action/event is generated. 0x1:Error Raw Mode Enabled. RX_ERR is not qualified with RX_DV, meaning RX_ERR action/event is generated even if RX_DV = 0. | RW | 0x0 |
7 | RX_SFD_RAW | 0x0: SFD Raw Mode Disabled. RX_SFD requires a pattern of D5. 0x1: SFD Raw Mode Enable. The first byte of any pattern after RX_DV assertion will trigger RX_SFD event. The first nibble of the frame (RX_DV = 1) will be in the RX FIFO. | RW | 0x0 |
6 | RX_AUTO_FWD_PRE | Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE. | RW | 0x0 |
5 | RX_BYTE_SWAP | Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order | RW | 0x0 |
4 | RX_L2_EN | Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable | RW | 0x0 |
3 | RX_MUX_SEL | Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1) | RW | 0x0 |
2 | RX_CUT_PREAMBLE | Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA | RW | 0x0 |
1 | RX_DATA_RDY_MODE_DIS | 0x0: R31, Bit 16 is configured for DATA_RDY mode. 0x1: R31, Bit 16 is configured for TX_EOF mode. | RW | 0x0 |
0 | RX_ENABLE | Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable | RW | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4B23 2004 0x4B2B 2004 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | This register contains the PRU1 RXCFG configuration variables (PRUSS_MII_RT_RXCFG1) for the RX path. PRUSS_MII_RT_RXCFG1 is attached to PRU1. PRUSS_MII_RT_RXCFG1 controls which RX port is attached to PRU1 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_L2_EOF_SCLR_DIS | RX_ERR_RAW | RX_SFD_RAW | RX_AUTO_FWD_PRE | RX_BYTE_SWAP | RX_L2_EN | RX_MUX_SEL | RX_CUT_PREAMBLE | RX_DATA_RDY_MODE_DIS | RX_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x000000 | |
9 | RX_L2_EOF_SCLR_DIS | 0x0: RX_EOF flag in R31 and RXL2 is self cleared by hardware when RXL2 is enabled 0x1: RX_EOF flag in R31 and RXL2 is not self cleared by hardware when RXL2 is enabled. To clear this flag, RX_EOF_CLR must be set. | RW | 0x0 |
8 | RX_ERR_RAW | 0x0: Error Raw Mode Disabled. RX_ERR is qualified with RX_DV, meaning RX_DV = 1 before RX_ERR action/event is generated. 0x1: Error Raw Mode Enabled. RX_ERR is not qualified with RX_DV, meaning RX_ERR action/event is generated even if RX_DV = 0. | RW | 0x0 |
7 | RX_SFD_RAW | 0x0: SFD Raw Mode Disabled. RX_SFD requires a pattern of D5. 0x1: SFD Raw Mode Enable. The first byte of any pattern after RX_DV assertion will trigger RX_SFD event. The first nibble of the frame (RX_DV = 1) will be in the RX FIFO. | RW | 0x0 |
6 | RX_AUTO_FWD_PRE | Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE | RW | 0x0 |
5 | RX_BYTE_SWAP | Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. | RW | 0x0 |
4 | RX_L2_EN | Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable | RW | 0x0 |
3 | RX_MUX_SEL | Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1) | RW | 0x1 |
2 | RX_CUT_PREAMBLE | Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address. | RW | 0x0 |
1 | RX_DATA_RDY_MODE_DIS | 0x0: R31, Bit 16 is configured for DATA_RDY mode. 0x1: R31, Bit 16 is configured for TX_EOF mode. | RW | 0x0 |
0 | RX_ENABLE | Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable | RW | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0010 | ||
Physical Address | 0x4B23 2010 0x4B2B 2010 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | This register contains the configuration variables for the transmit path on the MII interface port 0. PRUSS_MII_RT_TXCFG0 is attached to Port TX0. PRUSS_MII_RT_TXCFG0 controls which PRU is selected for TX0 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_CLK_DELAY | RESERVED | TX_START_DELAY | RESERVED | TX_32_MODE_EN | RESERVED | TX_AUTO_SEQUENCE | TX_MUX_SEL | RESERVED | TX_BYTE_SWAP | TX_EN_MODE | TX_AUTO_PREAMBLE | TX_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | R | 0 | |
30:28 | TX_CLK_DELAY | In order to guarantee the MII_RT IO timing values published in the device Data Manual, the PRUSS_GICLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY bitfield must be configured as follows: - 100 Mbps mode: 6h (non-default value) - 10 Mbps mode: 0h (default value) | RW | 0x0 |
27:26 | RESERVED | R | 0x0 | |
25:16 | TX_START_DELAY | Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 96-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration. | RW | 0x40 |
15:12 | RESERVED | R | 0x0 | |
11 | TX_32_MODE_EN | 0x0 Disable 32-bit Data Push mode 0x1 Enable 32-bit, 16-bit, and 8-bit Data Push mode with TX_MASK disabled. In this mode, the internal PRU R30 byte write strobes are used and not the R31 CMD TX_PUSH mode. Any update to R30 will trigger an TX PUSH. See Table 30-278 | RW | 0x0 |
10 | RESERVED | R | 0x0 | |
9 | TX_AUTO_SEQUENCE | Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used. | RW | 0x0 |
8 | TX_MUX_SEL | Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0) | RW | 0x1 |
7:4 | RESERVED | R | 0x0 | |
3 | TX_BYTE_SWAP | Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte1{Nibble3,Nibble2} R30[7:0] = Byte0{Nibble1,Nibble0} R30[31:24] = TX_MASK[15:8] R30[23:16] = TX_MASK[7:0] If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 1, R30[31:24] = Byte3{Nibble7,Nibble6} R30[23:16] = Byte2{Nibble5,Nibble4} R30[15:8] = Byte1{Nibble3,Nibble2} R30[ 7:0] = Byte0{Nibble1,Nibble0} 0x1: If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte0{Nibble1,Nibble0} R30[7:0] = Byte1{Nibble3,Nibble2} R30[31:24] = TX_MASK[7:0] R30[23:16] = TX_MASK[15:8] If PRUSS_MII_RT_TXCFG0/1[TX_32_MODE_EN] = 1, (ONLY SUPPORT 32bit push) R30[31:24] = Byte0{Nibble1,Nibble0} R30[23:16] = Byte1{Nibble3,Nibble2} R30[15:8] = Byte2{Nibble5,Nibble4} R30[ 7:0] = Byte3{Nibble7,Nibble6 Note Nibble0 is the first nibble received. | RW | 0x0 |
2 | TX_EN_MODE | Enables transmit self clear on TX_EOF event. Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself. | RW | 0x0 |
1 | TX_AUTO_PREAMBLE | Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency. | RW | 0x0 |
0 | TX_ENABLE | Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired | RW | 0x0 |
PRU-ICSS MII RT Module |
PRU-ICSS Industrial Ethernet Peripheral (IEP) |
Address Offset | 0x0000 0014 | ||
Physical Address | 0x4B23 2014 0x4B2B 2014 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. PRUSS_MII_RT_TXCFG1 is attached to Port TX1. PRUSS_MII_RT_TXCFG1 controls which PRU is selected for TX1 | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_CLK_DELAY | RESERVED | TX_START_DELAY | RESERVED | TX_32_MODE_EN | RESERVED | TX_AUTO_SEQUENCE | TX_MUX_SEL | RESERVED | TX_BYTE_SWAP | TX_EN_MODE | TX_AUTO_PREAMBLE | TX_ENABLE |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | RESERVED | R | 0 | |
30:28 | TX_CLK_DELAY | In order to guarantee the MII_RT IO timing values published in the device Data Manual, the PRUSS_GICLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY bitfield must be configured as follows: - 100 Mbps mode: 6h (non-default value) - 10 Mbps mode: 0h (default value). | RW | 0x0 |
27:26 | RESERVED | R | 0x0 | |
25:16 | TX_START_DELAY | Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 96-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration. | RW | 0x40 |
15:12 | RESERVED | R | 0x0 | |
11 | TX_32_MODE_EN | 0x0 Disable 32-bit Data Push mode 0x1 Enable 32-bit, 16-bit, and 8-bit Data Push mode with TX_MASK disabled. In this mode, the internal PRU R30 byte write strobes are used and not the R31 CMD TX_PUSH mode. Any update to R30 will trigger an TX PUSH. See Table Table 30-278 | RW | 0x0 |
10 | RESERVED | R | 0x0 | |
9 | TX_AUTO_SEQUENCE | Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used. | RW | 0x0 |
8 | TX_MUX_SEL | Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0) | RW | 0x0 |
7:4 | RESERVED | R | 0x0 | |
3 | TX_BYTE_SWAP | Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte1{Nibble3,Nibble2} R30[7:0] = Byte0{Nibble1,Nibble0} R30[31:24] = TX_MASK[15:8] R30[23:16] = TX_MASK[7:0] If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 1, R30[31:24] = Byte3{Nibble7,Nibble6} R30[23:16] = Byte2{Nibble5,Nibble4} R30[15:8] = Byte1{Nibble3,Nibble2} R30[ 7:0] = Byte0{Nibble1,Nibble0} 0x1: If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte0{Nibble1,Nibble0} R30[7:0] = Byte1{Nibble3,Nibble2} R30[31:24] = TX_MASK[7:0] R30[23:16] = TX_MASK[15:8] If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 1, (ONLY SUPPORT 32bit push) R30[31:24] = Byte0{Nibble1,Nibble0} R30[23:16] = Byte1{Nibble3,Nibble2} R30[15:8] = Byte2{Nibble5,Nibble4} R30[ 7:0] = Byte3{Nibble7,Nibble6 Note Nibble0 is the first nibble received. | RW | 0x0 |
2 | TX_EN_MODE | Enables transmit self clear on TX_EOF event. Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself. | RW | 0x0 |
1 | TX_AUTO_PREAMBLE | Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency. | RW | 0x0 |
0 | TX_ENABLE | Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired | RW | 0x0 |
PRU-ICSS MII RT Module |
PRU-ICSS Industrial Ethernet Peripheral (IEP) |
Address Offset | 0x0000 0020 | ||
Physical Address | 0x4B23 2020 0x4B2B 2020 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII TXCRC 0 REGISTER
It contains CRC32 which PRU0 reads | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_CRC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TX_CRC | FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given. | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4B23 2024 0x4B2B 2024 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII TXCRC 1 REGISTER
It contains CRC32 which PRU1 reads | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_CRC |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:0 | TX_CRC | FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given. | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0030 | ||
Physical Address | 0x4B23 2030 0x4B2B 2030 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII TXIPG 0 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_IPG |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9:0 | TX_IPG | Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect. | RW | 0x28 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0034 | ||
Physical Address | 0x4B23 2034 0x4B2B 2034 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII TXIPG 1 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_IPG |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:10 | RESERVED | R | 0x0 | |
9:0 | TX_IPG | Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect. | RW | 0x28 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4B23 2038 0x4B2B 2038 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII PORT STATUS 0 REGISTER | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MII_CRS | MII_COL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1 | MII_CRS | Read the current state of pr1_mii0_crs | R | 0x0 |
0 | MII_COL | Read the current state of pr1_mii0_col | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 003C | ||
Physical Address | 0x4B23 203C 0x4B2B 203C | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII PORT STATUS 1 REGISTER | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MII_CRS | MII_COL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:2 | RESERVED | R | 0x0 | |
1 | MII_CRS | Read the current state of pr1_mii1_crs | R | 0x0 |
0 | MII_COL | Read the current state of pr1_mii1_col | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0040 | ||
Physical Address | 0x4B23 2040 0x4B2B 2040 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXFRMS 0 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MAX_FRM | RX_MIN_FRM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RX_MAX_FRM | Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted. | RW | 0x5F1 |
15:0 | RX_MIN_FRM | Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC | RW | 0x3F |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4B23 2044 0x4B2B 2044 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXFRMS 1 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_MAX_FRM | RX_MIN_FRM |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | RX_MAX_FRM | Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted. | RW | 0x5F1 |
15:0 | RX_MIN_FRM | Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC | RW | 0x3F |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0048 | ||
Physical Address | 0x4B23 2048 0x4B2B 2048 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXPCNT 0 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_PCNT | RX_MIN_PCNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x000000 | |
7:4 | RX_MAX_PCNT | Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble. | RW | 0xE |
3:0 | RX_MIN_PCNT | Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be “0x5” | RW | 0x1 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4B23 204C 0x4B2B 204C | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXPCNT 1 REGISTER | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_PCNT | RX_MIN_PCNT |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0x000000 | |
7:4 | RX_MAX_PCNT | Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble. | RW | 0xE |
3:0 | RX_MIN_PCNT | Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be “0x5” | RW | 0x1 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0050 | ||
Physical Address | 0x4B23 2050 0x4B2B 2050 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXERR 0 REGISTER | ||
Type | RWr1Clr |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_FRM_ERR | RX_MIN_FRM_ERR | RX_MAX_PCNT_ERR | RX_MIN_PCNT_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:4 | RESERVED | R | 0x00000 | |
3 | RX_MAX_FRM_ERR | Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RWr1Clr | 0x0 |
2 | RX_MIN_FRM_ERR | Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RWr1Clr | 0x0 |
1 | RX_MAX_PCNT_ERR | Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RWr1Clr | 0x0 |
0 | RX_MIN_PCNT_ERR | Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RWr1Clr | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4B23 2054 0x4B2B 2054 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII RXERR 1 REGISTER | ||
Type | RWr1Clr |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAX_FRM_ERR | RX_MIN_FRM_ERR | RX_MAX_PCNT_ERR | RX_MIN_PCNT_ERR |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:4 | RESERVED | R | 0x00000 | |
3 | RX_MAX_FRM_ERR | Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RW | 0x0 |
2 | RX_MIN_FRM_ERR | Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RW | 0x0 |
1 | RX_MAX_PCNT_ERR | Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RW | 0x0 |
0 | RX_MIN_PCNT_ERR | Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear | RW | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0060 | ||
Physical Address | 0x4B2B 2060 0x4B2B 2060 | Instance | PRUSS2_MII_RT PRUSS2_MII_RT |
Description | MII PRUSS_MII_RT_RXFLV0 REGISTER This register defines the number of valid bytes in the RX FIFO MII interface port 0. PRUSS_MII_RT_RXFLV0 is attached to Port RX0. PRUSS_MII_RT_RXFLV0 controls which PRU is selected for RX0 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_FIFO_LEVEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0 | |
7:0 | RX_FIFO_LEVEL | Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4B23 2064 0x4B2B 2064 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII PRUSS_MII_RT_RXFLV1 REGISTER This register defines the number of valid bytes in the RX FIFO MII interface port 1. PRUSS_MII_RT_RXFLV1 is attached to Port RX1. PRUSS_MII_RT_RXFLV1 controls which PRU is selected for RX1 | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_FIFO_LEVEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0 | |
7:0 | RX_FIFO_LEVEL | Define the number of valid bytes in the RX FIFO 0 = empty 1 = 1 Byte/ 2 Nibbles 2 = 2 Byte/ 4 Nibble ... 32 = 32 Bytes/ 64 Nibbles | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 0068 | ||
Physical Address | 0x4B23 2068 0x4B2B 2068 | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII PRUSS_MII_RT_TXFLV0 REGISTER This register defines the number of valid bytes in the TX FIFO MII interface port 0. PRUSS_MII_RT_TXFLV0 is attached to Port TX0. PRUSS_MII_RT_TXFLV0 controls which PRU is selected for TX0. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_FIFO_LEVEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0 | |
7:0 | TX_FIFO_LEVEL | Define the number of valid bytes in the TX FIFO 0 = empty 1 = 1 Nibbles 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles ... 192 = 96 Bytes/ 192 Nibbles | R | 0x0 |
PRU-ICSS MII RT Module |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4B23 206C 0x4B2B 206C | Instance | PRUSS1_MII_RT PRUSS2_MII_RT |
Description | MII PRUSS_MII_RT_TXFLV1 REGISTER This register defines the number of valid bytes in the TX FIFO MII interface port 1. PRUSS_MII_RT_TXFLV1 is attached to Port TX1. PRUSS_MII_RT_TXFLV1 controls which PRU is selected for TX1. | ||
Type | R |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_FIFO_LEVEL |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | RESERVED | R | 0 | |
7:0 | TX_FIFO_LEVEL | Define the number of valid bytes in the TX FIFO 0 = empty 1 = 1 Nibbles 2 = 1 Byte/ 2 Nibble ... 128 = 64 Bytes/ 128 Nibbles ... 192 = 96 Bytes/ 192 Nibbles | R | 0x0 |
PRU-ICSS MII RT Module |