SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Statistic collectors are internal masters that share the same master address as the master NIUs. These components compute the traffic statistics within a defined window and periodically report through the DEBUG interface. The key features of the statistic collector are:
Event detectors are programmed through the L3_STCOL_REQEVT and L3_STCOL_RSPEVT configuration registers for request and response ports, respectively. The following events can be identified:
Performance monitoring is enabled through the L3_STCOL_EN register. The L3_STCOL_SOFTEN register enables software to monitor the performance. Event muxes are programmed through the L3_STCOL_EVTMUX_SEL0 configuration register, which determines which port will be monitored by a filter configured by the filter registers (see Section 14.2.5.1.9).
Filters are programmed through the L3_STCOL_FILTER_i_GLOBALEN configuration register, along with additional selection criteria programmed through the mask/match registers (see Table 14-237). A filter can be configured to accept or reject:
Filter operation is programmed through the L3_STCOL_OP registers (see Table 14-237).
There are ten statistic collectors used to monitor the traffic on DRAM (EMIF1 and MA_MPU_P1), MPU, MMU, TPTC, VIP, DSP MDMA/EDMA, IVA, GPU, DSS, IPU, OCMC RAM, PCIe Subsystem, VCP, DSP CFG and GPMC ports. For more detailed descriptions of statistic collectors, see Section 34.10.6.1, L3 Target Load Monitoring, and Section 34.10.6.2, Master Latency Monitoring.