SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Table 24-325 describes the McASP pins, their corresponding signal names at device level and specifies their links to functions.
Module Pin Name | Device Level Signal Name | I/O(1) | Description | Module Pin Reset Value |
---|---|---|---|---|
McASP1 module | ||||
AXR0 | mcasp1_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp1_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp1_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp1_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
AXR4 | mcasp1_axr[4] | I/O | Audio transmit/receive data - channel 4 | HiZ |
AXR5 | mcasp1_axr[5] | I/O | Audio transmit/receive data - channel 5 | HiZ |
AXR6 | mcasp1_axr[6] | I/O | Audio transmit/receive data - channel 6 | HiZ |
AXR7 | mcasp1_axr[7] | I/O | Audio transmit/receive data - channel 7 | HiZ |
AXR8 | mcasp1_axr[8] | I/O | Audio transmit/receive data - channel 8 | HiZ |
AXR9 | mcasp1_axr[9] | I/O | Audio transmit/receive data - channel 9 | HiZ |
AXR10 | mcasp1_axr[10] | I/O | Audio transmit/receive data - channel 10 | HiZ |
AXR11 | mcasp1_axr[11] | I/O | Audio transmit/receive data - channel 11 | HiZ |
AXR12 | mcasp1_axr[12] | I/O | Audio transmit/receive data - channel 12 | HiZ |
AXR13 | mcasp1_axr[13] | I/O | Audio transmit/receive data - channel 13 | HiZ |
AXR14 | mcasp1_axr[14] | I/O | Audio transmit/receive data - channel 14 | HiZ |
AXR15 | mcasp1_axr[15] | I/O | Audio transmit/receive data - channel 15 | HiZ |
ACLKX | mcasp1_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp1_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp1_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp1_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp1_fsr | I/O | Receive frame synchronization | HiZ |
McASP2 module | ||||
AXR0 | mcasp2_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp2_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp2_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp2_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
AXR4 | mcasp2_axr[4] | I/O | Audio transmit/receive data - channel 4 | HiZ |
AXR5 | mcasp2_axr[5] | I/O | Audio transmit/receive data - channel 5 | HiZ |
AXR6 | mcasp2_axr[6] | I/O | Audio transmit/receive data - channel 6 | HiZ |
AXR7 | mcasp2_axr[7] | I/O | Audio transmit/receive data - channel 7 | HiZ |
AXR8 | mcasp2_axr[8] | I/O | Audio transmit/receive data - channel 8 | HiZ |
AXR9 | mcasp2_axr[9] | I/O | Audio transmit/receive data - channel 9 | HiZ |
AXR10 | mcasp2_axr[10] | I/O | Audio transmit/receive data - channel 10 | HiZ |
AXR11 | mcasp2_axr[11] | I/O | Audio transmit/receive data - channel 11 | HiZ |
AXR12 | mcasp2_axr[12] | I/O | Audio transmit/receive data - channel 12 | HiZ |
AXR13 | mcasp2_axr[13] | I/O | Audio transmit/receive data - channel 13 | HiZ |
AXR14 | mcasp2_axr[14] | I/O | Audio transmit/receive data - channel 14 | HiZ |
AXR15 | mcasp2_axr[15] | I/O | Audio transmit/receive data - channel 15 | HiZ |
ACLKX | mcasp2_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp2_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp2_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp2_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp2_fsr | I/O | Receive frame synchronization | HiZ |
McASP3 module | ||||
AXR0 | mcasp3_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp3_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp3_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp3_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp3_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp3_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp3_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp3_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp3_fsr | I/O | Receive frame synchronization | HiZ |
McASP4 module | ||||
AXR0 | mcasp4_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp4_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp4_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp4_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp4_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp4_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp4_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp4_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp4_fsr | I/O | Receive frame synchronization | HiZ |
McASP5 module | ||||
AXR0 | mcasp5_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp5_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp5_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp5_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp5_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp5_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp5_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp5_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp5_fsr | I/O | Receive frame synchronization | HiZ |
McASP6 module | ||||
AXR0 | mcasp6_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp6_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp6_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp6_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp6_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp6_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp6_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp6_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp6_fsr | I/O | Receive frame synchronization | HiZ |
McASP7 module | ||||
AXR0 | mcasp7_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp7_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp7_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp7_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp7_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp7_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp7_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp7_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp7_fsr | I/O | Receive frame synchronization | HiZ |
McASP8 module | ||||
AXR0 | mcasp8_axr[0] | I/O | Audio transmit/receive data - channel 0 | HiZ |
AXR1 | mcasp8_axr[1] | I/O | Audio transmit/receive data - channel 1 | HiZ |
AXR2 | mcasp8_axr[2] | I/O | Audio transmit/receive data - channel 2 | HiZ |
AXR3 | mcasp8_axr[3] | I/O | Audio transmit/receive data - channel 3 | HiZ |
ACLKX | mcasp8_aclkx | I/O | Transmit bit clock | HiZ |
AHCLKX | mcasp8_ahclkx | O | Transmit high-frequency master clock | HiZ |
AFSX | mcasp8_fsx | I/O | Transmit frame synchronization | HiZ |
ACLKR | mcasp8_aclkr | I/O | Receive bit clock | HiZ |
AFSR | mcasp8_fsr | I/O | Receive frame synchronization | HiZ |
For the mcaspx_aclkx, mcaspx_ahclkx and mcaspx_aclkr signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers should be set to 0x1 because of retiming purposes.
The path from module pin to device pad(s) is defined at the device I/O logic level. The I/O logic maps the module signals to the different pads of the device and is programmable in the Control Module registers. For more information, refer to the Pad Configuration Registers, and Control Module Register Manual, in Control Module.
A serializer AXR data pin is shared between the transmit and receive logic of that serializer. The direction of data is determined in the MCASP_PDIR and the function (Tx or Rx) is selected in the corresponding serializer control register MCASP_XRSRCTLn.