SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
In this section is described configuration and settings of FIFO trigger level, which enable DMA and interrupt generation.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Configure register submode TCR_TLR | see Table 24-119 | 0x- |
Set the desire RX FIFO trigger level | UART_FCR[5:4] TX_FIFO_TRIG | 0x- |
Set the desire TX FIFO trigger level | UART_FCR[7:6] RX_FIFO_TRIG | 0x- |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Configure register submode TCR_TLR | see Table 24-119 | 0x- |
Set the desire RX FIFO trigger level | UART_TLR[7:4] RX_FIFO_TRIG_DMA | 0x- |
Set the desire TX FIFO trigger level | UART_TLR[3:0] TX_FIFO_TRIG_DMA | 0x- |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Configure register submode TCR_TLR | see Table 24-119 | 0x- |
Set the register bit | UART_SCR[7] RX_TRIG_GRANU1 | 1 |
Set the desire RX FIFO trigger level | UART_TLR[7:4] RX_FIFO_TRIG_DMA | 0x- |
UART_FCR[7:6] RX_FIFO_TRIG | ||
Set the register bit | UART_SCR[6] TX_TRIG_GRANU1 | 1 |
Set the desire TX FIFO trigger level | UART_TLR[3:0] TX_FIFO_TRIG_DMA | 0x- |
UART_FCR[5:4] TX_FIFO_TRIG |