SPRUI30H November 2015 – May 2024 DRA745 , DRA746 , DRA750 , DRA756
Table 15-419 describes the GPMC clocks.
Signal | I/O(1) | Description |
---|---|---|
GPMC_FCLK | I | Functional and interface clock |
gpmc_clk | O | External clock provided to synchronous external memory devices |
The gpmc_clk is generated by the GPMC from the internal GPMC_FCLK clock. The source of the GPMC_FCLK is described in Table 15-417. The gpmc_clk is configured using the GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER bit field (where i = 0 to 7), as shown in Table 15-420.
Source Clock | GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER | gpmc_clk Generated Clock Provided to External Memory Device |
---|---|---|
GPMC_FCLK | 00 | GPMC_FCLK |
01 | GPMC_FCLK/2 | |
10 | GPMC_FCLK/3 | |
11 | GPMC_FCLK/4 |