SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The CAL module has one BYS port for data input (BYS_PI) and another BYS port for data output (BYS_PO).
The BYS ports are 4 × 16 bits wide and carry 4 or 0 pixels per cycle. Pixels are LSB aligned inside 16-bit containers on the bus.
Table 9-51 and Table 9-52 summarize the BYS ports interface signals.
Signal name | I/O | Description |
---|---|---|
BYS_PI_PCLK | I | Pixel clock received from the ISS ISP. Asynchronous from the functional clock. The mean pixel clock must be less or equal to the functional clock (CAL_FCLK). The base clock used to generate this pixel clock may be up to 304 MHz. |
BYS_PI_VS | I | Active during the 1st pixel of the frame |
BYS_PI_VE | I | Active during the last pixel of the frame |
BYS_PI_HS | I | Active during the 1st pixel of any line |
BYS_PI_HE | I | Active during the last pixel of any line |
BYS_PI_DATA[15:0] | I | Pixel data for position (X%4)=0. MSBs padded with 0s when less than 16 bits are used. |
BYS_PI_DATA[31:16] | I | Pixel data for position (X%4)=1. MSBs padded with 0s when less than 16 bits are used. |
BYS_PI_DATA[47:32] | I | Pixel data for position (X%4)=2. MSBs padded with 0s when less than 16 bits are used. |
BYS_PI_DATA[63:48] | I | Pixel data for position (X%4)=3. MSBs padded with 0s when less than 16 bits are used. |
Signal name | I/O | Description |
---|---|---|
BYS_PO_PCLK | O | Pixel clock provided to the ISS ISP. Synchronous to the functional clock. Mean clock rate defined by the CAL_BYS_CTRL1[16:10] PCLK bit field. |
BYS_PO_VS | O | Active during the 1st pixel of the frame |
BYS_PO_HS | O | Active during the 1st pixel of any line |
BYS_PO_DATA[15:0] | O | Pixel data for position (X%4)=0. MSBs padded with 0s when less than 16 bits are used. |
BYS_PO_DATA[31:16] | O | Pixel data for position (X%4)=1. MSBs padded with 0s when less than 16 bits are used. |
BYS_PO_DATA[47:32] | O | Pixel data for position (X%4)=2. MSBs padded with 0s when less than 16 bits are used. |
BYS_PO_DATA[63:48] | O | Pixel data for position (X%4)=3. MSBs padded with 0s when less than 16 bits are used. |
The BYS input video port is asynchronous to the functional clock (CAL_FCLK). The DATA, HS, VS, HE and VE signals are sampled on the rising edge of BYS_PI_PCLK.
The BYS output video port is synchronous to CAL_FCLK clock. The data rate is imposed by the data arrival rate from memory. Software can impose a minimum time between two consecutive clock pulses using the CAL_BYS_CTRL1[16:10] PCLK bit field. It can also impose blanking times with active pixel clock using the CAL_BYS_CTRL1[24:17] XBLK and CAL_BYS_CTRL1[30:25] YBLK bit fields. The DATA, HS and VS signals are generated on the functional clock (CAL_FCLK) cycle before the next BYS_PO_PCLK edge. The BYS port is therefore timed for full functional clock speed.
Figure 9-8 and Table 9-53 provide examples for BYS input port timings and pixel data transaction.
Cycle Number | HS | HE | VS | VE | DATA [11:0] | DATA [15:12] | DATA [27:16] | DATA [31:28] | DATA [43:32] | DATA [47:44] | DATA [59:48] | DATA [63:60] |
---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 0 | 0 | 0 | 0 | Any Data | |||||||
2 | 0 | 0 | 0 | 0 | Any Data | |||||||
3 | 0 | 0 | 0 | 0 | Any Data | |||||||
4 | 0 | 0 | 0 | 0 | Any Data | |||||||
5 | 1 | 0 | 1 | 0 | Pixel 0 | 0s | Pixel 1 | 0s | Pixel 2 | 0s | Pixel 3 | 0s |
6 | 0 | 0 | 0 | 0 | Pixel 4 | 0s | Pixel 5 | 0s | Pixel 6 | 0s | Pixel 7 | 0s |
N(1) | 0 | 1 | 0 | 0 | Last pixel | 0s | 0s | 0s | 0s | 0s | 0s | 0s |
The BYS_PI_PCLK/BYS_PO_PCLK pulses are not necessarily regularly spaced.
There must be at least four BYS_PI_PCLK/BYS_PO_PCLK pulses before the first pixel of a frame (that is, after reset) and there must be at least four BYS_PI_PCLK/BYS_PO_PCLK cycles of vertical blanking after the frame end. Therefore, there must be at least eight PCLK cycles between two consecutive frames.
More details about the BYS ports are provided in Section 9.2.3.13, CAL BYS Ports.