SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The programmer can choose one of four duty cycles for modulation pulses by setting the appropriate value in the UART3.UART_MDR2[5:4] CIR_PULSE_MODE bit field (1/4, 1/3, 5/12, or 1/2).
Figure 26-51 shows the CIR modulation duty cycles.
The transmission logic ensures that all pulses are transmitted completely (no cutoff during transmission). While transmitting continuous bytes back-to-back, no delay is inserted between 2 transmitted bytes. Thus, software must handle the delay between consecutively transmitted bytes if the receiving end requires it.