SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
McSPI module allows the transfer of one or several words, according to different modes:
For all these sequences, the host process contains the main process and the interrupt routines.
The interrupt routines are called on the interrupt signals or by an internal call if the module is used in polling mode.
Table 26-213 represents the main sequence which is common to all transfers.
In multi-channel master mode, the sequences of different channels can be run simultaneously.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS[channel x bits] | 0b1111 |
Write MCSPI_IRQENABLE to enable interrupts | MCSPI_IRQENABLE | 0x- |
Write MCSPI_CHxCONF to configure the channel | MCSPI_CHxCONF | 0x- |
Start the channel | MCSPI_CHxCTRL[0] EN | 1 |
Wait for the first write request (TX empty or DMA write) | ||
Write the transmitter register with data | MCSPI_TXx | 0x- |
Wait for the host event for end of transfer | ||
Stop the channel | MCSPI_CHxCTRL[0] EN | 0 |