SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Table 17-5 describes the DMM clocks.
Signal | I/O(1) | Description |
---|---|---|
DMM_CLK | I | Functional and interface clock |
The DMM is concerned with SDRC management and is in the MEMIF clock domain among the SDRCs. The DMM is a fully synchronous module, which uses the clock and clock-enable signals provided in the MEMIF clock domain to generate its interface and functional clocks.
To configure DMM_CLK control and settings, see Table 17-2.