SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
There are three FIFOs used when ECC mode is enabled. Each FIFO is four level deep. The FIFOs are the following:
The SEC FIFO stores the SRAM addresses at which a single error is detected. The FIFO is able to store up to four unique addresses of the single errors occured. If there are more than four single errors associated with unique addresses, then only the first four addresses are stored in the FIFO. In case of occurrence of multiple correctable errors, the addresses are stored in the order the errors occurred. The SEC FIFO can be optionally configured to store all addresses of the single errors occured including also the repeated addresses. This is done by setting to 0x0 the CFG_OCMC_ECC_ERROR[24] CFG_DISCARD_DUP_ADDR bit. The SEC FIFO can be cleared by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[0] CLEAR_SEC_ERR_CNT bit or by reding FIFO's content one by one through the STATUS_SEC_ERROR_TRACE[17:0] ADDRESS_128BIT bit field which points to the SEC FIFO. In addition, the STATUS_SEC_ERROR_TRACE[18] VALID bit shows whether the FIFO is empty or not. A value of 0x1 means that the SEC FIFO is not empty and valid address can be read.
The DED FIFO stores the SRAM addresses when a double error is detected. The FIFO is able to store up to four unique addresses, but it can also be configured to store the repeated addresses by setting to 0x0 the CFG_OCMC_ECC_ERROR[24] CFG_DISCARD_DUP_ADDR bit. The STATUS_DED_ERROR_TRACE[17:0] ADDRESS_128BIT bit field points to the DED FIFO. The STATUS_DED_ERROR_TRACE[18] VALID bit shows whether the FIFO is empty or not. The DED FIFO can be cleared by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[1] CLEAR_DED_ERR_CNT bit or by reading its content one by one through the STATUS_DED_ERROR_TRACE[17:0] ADDRESS_128BIT.
The ADDRERR FIFO stores the SRAM addresses where the single error occured is an addres error. The STATUS_ADDR_TRANSLATION_ERROR_TRACE[17:0] ADDRESS_128BIT bit field points to the ADDRERR FIFO. The STATUS_ADDR_TRANSLATION_ERROR_TRACE[18] VALID bit shows whether the FIFO is empty or not. The ADDRERR FIFO can be cleared by setting to 0x1 the CFG_OCMC_ECC_CLEAR_HIST[2] CLEAR_ADDR_ERR_CNT bit or by reading its content one by one through the STATUS_ADDR_TRANSLATION_ERROR_TRACE[17:0] ADDRESS_128BIT pointer. The ADDRERR FIFO is also able to store up to four unique addresses and can also be configured to store repeated addresses by setting to 0x0 the CFG_OCMC_ECC_ERROR[24] CFG_DISCARD_DUP_ADDR bit.