SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
When APLL_PCIE finishes calibration and lock sequences it enters a locked state. APLL_PCIE locked state is indicated by PRCM.CM_IDLEST_APLL_PCIE[0] ST_APLL_CLK bit asserted to 0b1. In locked mode all the parameters of DPLL_PCIE_REF are set and the loop is running. The output clocks CLKVCOLDO and CLKVCOLDO_DIV are active under software control.