SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The procedure in Table 26-354 configures the McASP pins for McASP functionality.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Configure module different pins to have McASP functionality. | MCASP_PFUNC[31:0] | 0x0 |
Configure the McASP pins direction: AFSX AHCLKX ACLKX Desired n-th McASP data pin AXRn is configured as an ouput for transmission. | MCASP_PDIR[28] AFSR; MCASP_PDIR[27] AHCLKR; MCASP_PDIR[26] ACLKR; MCASP_PDIR[n] AXRn | 0x-(1) 0x-(1) 0x- (1) 0x1 |