SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
At the ISS level, the VP is connected to the VP of the CAL_B interface module. The selection, which interface VP is connected to the ISP is done on ISS top level through ISS_VMUX register bit fields.
VP implementation differences force the introduction of a bridge between the CAL_B and the ISP VP. The role of the bridge is to perform VD pulse extension. The CAL_B module assumes that the VD signal is active for at least one pixel clock cycle, and the CAL_B module assumes that the VD signal is asserted for four pixel clock cycles. However, the ISP assumes that the VD pulse is active on at least one line.
Figure 9-30 shows how the VD pulse extension works. Assume that VD-IN is the VD signal at the input of the pulse extension bridge, and VD-OUT is the VD signal at the output of the pulse extension bridge.
VD-OUT is asserted at the same time as VD-IN. VD-OUT is kept high until one full line is received. A line is delimited by two rising edges of the HD signal. VD-OUT is deasserted on the next cycle after the falling edge of the HD signal.
The ISP5_CTRL[23] VD_PULSE_EXT bit controls whether the VD extension bridge is enabled or disabled. By default, the bridge is enabled. When the bridge is disabled, the VD pulse must be unmodified: VD-OUT = VD-IN. At the ISS level, it is expected that ISP5_CTRL[23] VD_PULSE_EXT = 1 when the VP gets data from the CAL_B module.
A minimum of four lines per frame is required on the VP when the VD pulse extension bridge is enabled; therefore, the VD extension bridge is not functional if a 1-/2-/3-line frame is sent to the VP.