SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Upon detection, the following error conditions generate interrupt flags:
In the transmit status register (MCASP_TXSTAT):
Each interrupt source also has a corresponding enable bit in the transmit interrupt control register (MCASP_EVTCTLX). If the enable bit is set, an interrupt is requested when the interrupt flag is set in MCASP_TXSTAT. If the enable bit is not set, no interrupt request is generated. However, the interrupt flag may be polled.
In the receive status register (MCASP_RXSTAT) :
Each interrupt source also has a corresponding enable bit in the receive interrupt control register (MCASP_EVTCTLR). If the enable bit is set, an interrupt is requested when the interrupt flag is set in MCASP_RXSTAT. If the enable bit is not set, no interrupt request is generated. However, the interrupt flag may be polled.