SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The McSPI controller has a built-in 128-byte buffer to unload the DMA or interrupt handler and improve data throughput.
This buffer can be used by only one channel at a time and is selected by setting the MCSPI_CHxCONF[28] FFER or MCSPI_CHxCONF[27] FFEW bit to 1. If several channels are selected and several FIFO enable bit fields are set to 1, the controller forces the buffer not to be used; the driver must set only one FIFO enable bit field.
The buffer can be used in the following modes:
Every word length ( MCSPI_CHxCONF[11:7] WL) is supported.
In transmit-and-receive mode, the buffer can be used in transmit (see Figure 26-91) or receive (see Figure 26-92) directions, or in both directions. If only one direction is chosen in transmit-and-receive mode, the full buffer is used for this direction. In both directions, the buffer is split into two halves, one for each direction (see Figure 26-93).
Two levels ( MCSPI_XFERLEVEL[5:0] AEL and MCSPI_XFERLEVEL[13:8] AFL) rule the buffer management. The granularity of these levels is 1 byte; it is not aligned with the SPI word length. The driver must set these values as a multiple of the SPI word length defined in MCSPI_CHxCONF[11:7] WL. Table 26-206 lists the number of bytes written in the FIFO, depending on the word length.
SPI Word Length (WL) | |||
---|---|---|---|
3 ≤ WL≤ 7 | 8 ≤ WL ≤ 15 | 16 ≤ WL ≤ 31 | |
Number of bytes written in the FIFO | 1 byte | 2 bytes | 4 bytes |
The FIFO buffer pointers are reset when the corresponding channel is enabled or the FIFO configuration changes.