SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The GPIO1 module of the general-purpose interface is attached to the WKUPAON power domain (see Power Management, in Power, Reset, and Clock Management, and can wake up the system.
The GPIO2 to GPIO8 modules belong to the PD_L4PER power domain and thus their wake-up capabilities are operational only when the PD_L4PER power domain is active.
All wake-up sources (the 32 input GPIO channels) are merged together to issue a single asynchronous wake-up request in each GPIO module following the expected transition(s) (based on register programming). Each GPIO module generates a wake-up signal to the PRCM module.
Only gpio1_[3:0] can be used to generate a direct wake-up event.
The asynchronous wake-up request line is active based on the GPIOi.GPIO_IRQWAKEN_0 and GPIO_IRQWAKEN_1 wake-up-enable registers (where i = 1 to 8).
The wake-up-enable register allows masking of the expected transition on input GPIO to prevent the generation of a wake-up request. The wake-up-enable register is programmed synchronously with the interface clock before any idle mode request coming from the host processor.
This register can be accessed with direct read/write operations.
There must be a correlation between the wake-up enable and interrupt-enable registers. If a GPIO pin has a wake-up configured on it, it must also have the corresponding interrupt enabled (on one of the two interrupt lines). Otherwise, it is possible to have a wake-up event, but after exiting the IDLE state, no interrupt is generated; thus, the corresponding bit from the interrupt status register is not cleared, and the module does not acknowledge a future IDLE request.
Table 29-9 lists the mapping of the wake-up signals.
Name | Mapping | Comments |
---|---|---|
GPIOi_WAKE | GPIOi_SWAKEUP | Where i = 1 to 8. The destination is the PRCM module. |