SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The procedures listed in Table 16-30 and Table 16-31 give information about the configuration of FLAGMUX masks.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Set the FLAGMUX masks to mask an event. | L3_FLAGMUX_MASK031:0] MASK0 L3_FLAGMUX_MASK1[31:0] MASK1 | xxx |
Read the REGERR bits to see if an error is recorded. | L3_FLAGMUX_REGERR0[31:0] REGERR0 L3_FLAGMUX_REGERR1[31:0] REGERR1 | xxx |
Clear the slave NIU error log and the FLAGMUX error. | L3_TARG_STDERRLOG_MAIN[31] STDERRLOG_SVRTSTDLVL_0 | 0x1 |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Enable time-out for target. | L3_FLAGMUX_TIMEOUTx_MASK0[24:0] MASK0 (1) | xxx |
Read the REGERR bits to see if an error is recorded. | L3_FLAGMUX_TIMEOUTx_REGERR0[24:0] REGERR0 (1) | xxx |
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Enable time-out for target. | L3_FLAGMUX_TIMEOUT_MASK0[1:0] MASK0 | xxx |
Read the REGERR bits to see if an error is recorded. | L3_FLAGMUX_TIMEOUT_REGERR0[1:0] REGERR0 | xxx |