SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
A sending device may use only a subset of the signals described in Section 11.4.5.6.4. The sending device just needs to convey important signals required to capture the field or frame. It can be shown that various selections of four pins can be used to satisfy all Type 1 conditions.
Three pins, VSYNC, ACTVID, and FID, plus a pixel clock can be used to support discrete sync. VSYNC would bump the capture buffer. An inactive to active level of ACTVID specifies a line of data to capture. FID determines the field ID polarity. The scenario in which the sending device wants the receiving end to capture Vertical Ancillary Data using 4-pin signaling is shown in Figure 11-31.
Figure 11-32 describes the case using the 4-pin interface in which the sending device does not send Vertical Ancillary Data.