SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
There are two clock domains in the watchdog timer:
Table 24-63 lists the source clocks for the watchdog timer in the device. For more information about clock control and domains, see Clock Management Functional Description, in Power, Reset, and Clock Management.
From a global system power-management perspective, when the watchdog timer clocks is no longer required, the watchdog timer can be deactivated at the PRCM module level in the corresponding registers.
At the PRCM module level, when the conditions to shut off the PRCM module functional or interface output clocks are met (for more information, see Clock Domain-Level Clock Management), the PRCM module automatically launches a hardware handshake protocol to ensure the watchdog timer is ready to have its clocks switched off. Namely, the PRCM module asserts an IDLE request to the watchdog timer.
Although this handshake is a hardware function and out of software control, the way on which the watchdog timer acknowledges the PRCM IDLE request is configurable through the WDSC[4:3] IDLEMODE bit field. Table 24-65 lists the settings and related acknowledgment modes of the IDLEMODE bit field.
IDLEMODE Value | Selected Mode | Description |
---|---|---|
00 | Force-idle | The watchdog timer unconditionally acknowledges the IDLE request from the PRCM module, regardless of its internal operations. This mode must be used carefully, because it does not prevent loss of data when the clock is switched off. |
01 | No-idle | The watchdog timer never acknowledges an IDLE request from the PRCM module. This mode is safe from a module point of view, because it ensures that the clocks remain active. It is not efficient from a power-saving perspective, however, because it does not allow the PRCM module output clock to be shut off and thus the power domain to be set to a lower power state. |
10 | Smart-idle | The watchdog timer acknowledges the IDLE request, basing its decision on its internal activity. The acknowledge signal is asserted only when all pending transactions and IRQ requests are treated. This is the best approach for efficient system power management. |
11 | Smart-idle wakeup-capable mode | The watchdog timer acknowledges the IDLE request, basing its decision on its internal activity. The timer generates (IRQ-request-related) wake-up events when in IDLE state if the WIRQWAKEEN[1:0] bit field is set to 1. |